1 /* mtpr.h 4.3 81/02/19 */ 2 3 /* 4 * VAX processor register numbers 5 */ 6 7 #define KSP 0 /* kernel stack pointer */ 8 #define ESP 1 /* exec stack pointer */ 9 #define SSP 2 /* supervisor stack pointer */ 10 #define USP 3 /* user stack pointer */ 11 #define ISP 4 /* interrupt stack pointer */ 12 #define P0BR 8 /* p0 base register */ 13 #define P0LR 9 /* p0 length register */ 14 #define P1BR 10 /* p1 base register */ 15 #define P1LR 11 /* p1 length register */ 16 #define SBR 12 /* system segment base register */ 17 #define SLR 13 /* system segment length register */ 18 #define PCBB 16 /* process control block base */ 19 #define SCBB 17 /* system control block base */ 20 #define IPL 18 /* interrupt priority level */ 21 #define ASTLVL 19 /* async. system trap level */ 22 #define SIRR 20 /* software interrupt request */ 23 #define SISR 21 /* software interrupt summary */ 24 #define ICCS 24 /* interval clock control */ 25 #define NICR 25 /* next interval count */ 26 #define ICR 26 /* interval count */ 27 #define TODR 27 /* time of year (day) */ 28 #define RXCS 32 /* console receiver control and status */ 29 #define RXDB 33 /* console receiver data buffer */ 30 #define TXCS 34 /* console transmitter control and status */ 31 #define TXDB 35 /* console transmitter data buffer */ 32 #define MAPEN 56 /* memory management enable */ 33 #define TBIA 57 /* translation buffer invalidate all */ 34 #define TBIS 58 /* translation buffer invalidate single */ 35 #define PMR 61 /* performance monitor enable */ 36 #define SID 62 /* system identification */ 37 38 #if VAX==780 39 #define ACCS 40 /* accelerator control and status */ 40 #define ACCR 41 /* accelerator maintenance */ 41 #define WCSA 44 /* WCS address */ 42 #define WCSD 45 /* WCS data */ 43 #define SBIFS 48 /* SBI fault and status */ 44 #define SBIS 49 /* SBI silo */ 45 #define SBISC 50 /* SBI silo comparator */ 46 #define SBIMT 51 /* SBI maintenance */ 47 #define SBIER 52 /* SBI error register */ 48 #define SBITA 53 /* SBI timeout address */ 49 #define SBIQC 54 /* SBI quadword clear */ 50 #define MBRK 60 /* micro-program breakpoint */ 51 #endif 52 53 #if VAX==750 54 #define CSRS 0x1c /* console storage receive status register */ 55 #define CSRD 0x1d /* console storage receive data register */ 56 #define CSTS 0x1e /* console storage transmit status register */ 57 #define CSTD 0x1f /* console storage transmit data register */ 58 #define TBDR 0x24 /* translation buffer disable register */ 59 #define CADR 0x25 /* cache disable register */ 60 #define MCESR 0x26 /* machine check error summary register */ 61 #define CAER 0x27 /* cache error */ 62 #define IUR 0x37 /* init unibus register */ 63 #define TB 0x3b /* translation buffer */ 64 #endif 65