1*2612Swnj /* mtpr.h 4.4 81/02/21 */ 262Sbill 362Sbill /* 462Sbill * VAX processor register numbers 562Sbill */ 662Sbill 7*2612Swnj #define KSP 0x0 /* kernel stack pointer */ 8*2612Swnj #define ESP 0x1 /* exec stack pointer */ 9*2612Swnj #define SSP 0x2 /* supervisor stack pointer */ 10*2612Swnj #define USP 0x3 /* user stack pointer */ 11*2612Swnj #define ISP 0x4 /* interrupt stack pointer */ 12*2612Swnj #define P0BR 0x8 /* p0 base register */ 13*2612Swnj #define P0LR 0x9 /* p0 length register */ 14*2612Swnj #define P1BR 0xa /* p1 base register */ 15*2612Swnj #define P1LR 0xb /* p1 length register */ 16*2612Swnj #define SBR 0xc /* system segment base register */ 17*2612Swnj #define SLR 0xd /* system segment length register */ 18*2612Swnj #define PCBB 0x10 /* process control block base */ 19*2612Swnj #define SCBB 0x11 /* system control block base */ 20*2612Swnj #define IPL 0x12 /* interrupt priority level */ 21*2612Swnj #define ASTLVL 0x13 /* async. system trap level */ 22*2612Swnj #define SIRR 0x14 /* software interrupt request */ 23*2612Swnj #define SISR 0x15 /* software interrupt summary */ 24*2612Swnj #define ICCS 0x18 /* interval clock control */ 25*2612Swnj #define NICR 0x19 /* next interval count */ 26*2612Swnj #define ICR 0x1a /* interval count */ 27*2612Swnj #define TODR 0x1b /* time of year (day) */ 28*2612Swnj #define RXCS 0x20 /* console receiver control and status */ 29*2612Swnj #define RXDB 0x21 /* console receiver data buffer */ 30*2612Swnj #define TXCS 0x22 /* console transmitter control and status */ 31*2612Swnj #define TXDB 0x23 /* console transmitter data buffer */ 32*2612Swnj #define MAPEN 0x38 /* memory management enable */ 33*2612Swnj #define TBIA 0x39 /* translation buffer invalidate all */ 34*2612Swnj #define TBIS 0x3a /* translation buffer invalidate single */ 35*2612Swnj #define PMR 0x3d /* performance monitor enable */ 36*2612Swnj #define SID 0x3e /* system identification */ 3762Sbill 381907Swnj #if VAX==780 39*2612Swnj #define ACCS 0x28 /* accelerator control and status */ 40*2612Swnj #define ACCR 0x29 /* accelerator maintenance */ 41*2612Swnj #define WCSA 0x2c /* WCS address */ 42*2612Swnj #define WCSD 0x2d /* WCS data */ 43*2612Swnj #define SBIFS 0x30 /* SBI fault and status */ 44*2612Swnj #define SBIS 0x31 /* SBI silo */ 45*2612Swnj #define SBISC 0x32 /* SBI silo comparator */ 46*2612Swnj #define SBIMT 0x33 /* SBI maintenance */ 47*2612Swnj #define SBIER 0x34 /* SBI error register */ 48*2612Swnj #define SBITA 0x35 /* SBI timeout address */ 49*2612Swnj #define SBIQC 0x36 /* SBI quadword clear */ 50*2612Swnj #define MBRK 0x3c /* micro-program breakpoint */ 511907Swnj #endif 521907Swnj 531907Swnj #if VAX==750 54*2612Swnj #define MCSR 0x17 /* machine check status register */ 551907Swnj #define CSRS 0x1c /* console storage receive status register */ 561907Swnj #define CSRD 0x1d /* console storage receive data register */ 571907Swnj #define CSTS 0x1e /* console storage transmit status register */ 581907Swnj #define CSTD 0x1f /* console storage transmit data register */ 591907Swnj #define TBDR 0x24 /* translation buffer disable register */ 601907Swnj #define CADR 0x25 /* cache disable register */ 611907Swnj #define MCESR 0x26 /* machine check error summary register */ 621907Swnj #define CAER 0x27 /* cache error */ 631907Swnj #define IUR 0x37 /* init unibus register */ 641907Swnj #define TB 0x3b /* translation buffer */ 651907Swnj #endif 66