123268Smckusick /* 223268Smckusick * Copyright (c) 1982 Regents of the University of California. 323268Smckusick * All rights reserved. The Berkeley software License Agreement 423268Smckusick * specifies the terms and conditions for redistribution. 523268Smckusick * 6*24178Sbloom * @(#)mtpr.h 6.3 (Berkeley) 08/05/85 723268Smckusick */ 862Sbill 962Sbill /* 1062Sbill * VAX processor register numbers 1162Sbill */ 1262Sbill 132612Swnj #define KSP 0x0 /* kernel stack pointer */ 142612Swnj #define ESP 0x1 /* exec stack pointer */ 152612Swnj #define SSP 0x2 /* supervisor stack pointer */ 162612Swnj #define USP 0x3 /* user stack pointer */ 172612Swnj #define ISP 0x4 /* interrupt stack pointer */ 182612Swnj #define P0BR 0x8 /* p0 base register */ 192612Swnj #define P0LR 0x9 /* p0 length register */ 202612Swnj #define P1BR 0xa /* p1 base register */ 212612Swnj #define P1LR 0xb /* p1 length register */ 222612Swnj #define SBR 0xc /* system segment base register */ 232612Swnj #define SLR 0xd /* system segment length register */ 242612Swnj #define PCBB 0x10 /* process control block base */ 252612Swnj #define SCBB 0x11 /* system control block base */ 262612Swnj #define IPL 0x12 /* interrupt priority level */ 272612Swnj #define ASTLVL 0x13 /* async. system trap level */ 282612Swnj #define SIRR 0x14 /* software interrupt request */ 292612Swnj #define SISR 0x15 /* software interrupt summary */ 302612Swnj #define ICCS 0x18 /* interval clock control */ 312612Swnj #define NICR 0x19 /* next interval count */ 322612Swnj #define ICR 0x1a /* interval count */ 332612Swnj #define TODR 0x1b /* time of year (day) */ 342612Swnj #define RXCS 0x20 /* console receiver control and status */ 352612Swnj #define RXDB 0x21 /* console receiver data buffer */ 362612Swnj #define TXCS 0x22 /* console transmitter control and status */ 372612Swnj #define TXDB 0x23 /* console transmitter data buffer */ 382612Swnj #define MAPEN 0x38 /* memory management enable */ 392612Swnj #define TBIA 0x39 /* translation buffer invalidate all */ 402612Swnj #define TBIS 0x3a /* translation buffer invalidate single */ 412612Swnj #define PMR 0x3d /* performance monitor enable */ 422612Swnj #define SID 0x3e /* system identification */ 4362Sbill 44*24178Sbloom #if defined(VAX780) || defined(VAX8600) 45*24178Sbloom #define ACCS 0x28 /* accelerator control and status */ 46*24178Sbloom #endif 47*24178Sbloom 48*24178Sbloom #if defined(VAX8600) 49*24178Sbloom #define TBCHK 0x3f /* Translation Buffer Check */ 50*24178Sbloom #define PAMACC 0x40 /* PAMM access */ 51*24178Sbloom #define PAMLOC 0x41 /* PAMM location */ 52*24178Sbloom #define CSWP 0x42 /* Cache sweep */ 53*24178Sbloom #define MDECC 0x43 /* MBOX data ecc register */ 54*24178Sbloom #define MENA 0x44 /* MBOX error enable register */ 55*24178Sbloom #define MDCTL 0x45 /* MBOX data control register */ 56*24178Sbloom #define MCCTL 0x46 /* MBOX mcc control register */ 57*24178Sbloom #define MERG 0x47 /* MBOX error generator register */ 58*24178Sbloom #define CRBT 0x48 /* Console reboot */ 59*24178Sbloom #define DFI 0x49 /* Diag fault insertion register */ 60*24178Sbloom #define EHSR 0x4a /* Error handling status register */ 61*24178Sbloom #define STXCS 0x4c /* Console block storage C/S */ 62*24178Sbloom #define STXDB 0x4d /* Console block storage D/B */ 63*24178Sbloom #define ESPA 0x4e /* EBOX scratchpad address */ 64*24178Sbloom #define ESPD 0x4f /* EBOX sratchpad data */ 65*24178Sbloom #endif 66*24178Sbloom 6713864Ssam #if defined(VAX780) 682612Swnj #define ACCR 0x29 /* accelerator maintenance */ 692612Swnj #define WCSA 0x2c /* WCS address */ 702612Swnj #define WCSD 0x2d /* WCS data */ 712612Swnj #define SBIFS 0x30 /* SBI fault and status */ 722612Swnj #define SBIS 0x31 /* SBI silo */ 732612Swnj #define SBISC 0x32 /* SBI silo comparator */ 742612Swnj #define SBIMT 0x33 /* SBI maintenance */ 752612Swnj #define SBIER 0x34 /* SBI error register */ 762612Swnj #define SBITA 0x35 /* SBI timeout address */ 772612Swnj #define SBIQC 0x36 /* SBI quadword clear */ 782612Swnj #define MBRK 0x3c /* micro-program breakpoint */ 791907Swnj #endif 801907Swnj 8113864Ssam #if defined(VAX750) || defined(VAX730) 822612Swnj #define MCSR 0x17 /* machine check status register */ 831907Swnj #define CSRS 0x1c /* console storage receive status register */ 841907Swnj #define CSRD 0x1d /* console storage receive data register */ 851907Swnj #define CSTS 0x1e /* console storage transmit status register */ 861907Swnj #define CSTD 0x1f /* console storage transmit data register */ 871907Swnj #define TBDR 0x24 /* translation buffer disable register */ 881907Swnj #define CADR 0x25 /* cache disable register */ 891907Swnj #define MCESR 0x26 /* machine check error summary register */ 901907Swnj #define CAER 0x27 /* cache error */ 911907Swnj #define IUR 0x37 /* init unibus register */ 921907Swnj #define TB 0x3b /* translation buffer */ 931907Swnj #endif 94