1*23268Smckusick /* 2*23268Smckusick * Copyright (c) 1982 Regents of the University of California. 3*23268Smckusick * All rights reserved. The Berkeley software License Agreement 4*23268Smckusick * specifies the terms and conditions for redistribution. 5*23268Smckusick * 6*23268Smckusick * @(#)mtpr.h 6.2 (Berkeley) 06/08/85 7*23268Smckusick */ 862Sbill 962Sbill /* 1062Sbill * VAX processor register numbers 1162Sbill */ 1262Sbill 132612Swnj #define KSP 0x0 /* kernel stack pointer */ 142612Swnj #define ESP 0x1 /* exec stack pointer */ 152612Swnj #define SSP 0x2 /* supervisor stack pointer */ 162612Swnj #define USP 0x3 /* user stack pointer */ 172612Swnj #define ISP 0x4 /* interrupt stack pointer */ 182612Swnj #define P0BR 0x8 /* p0 base register */ 192612Swnj #define P0LR 0x9 /* p0 length register */ 202612Swnj #define P1BR 0xa /* p1 base register */ 212612Swnj #define P1LR 0xb /* p1 length register */ 222612Swnj #define SBR 0xc /* system segment base register */ 232612Swnj #define SLR 0xd /* system segment length register */ 242612Swnj #define PCBB 0x10 /* process control block base */ 252612Swnj #define SCBB 0x11 /* system control block base */ 262612Swnj #define IPL 0x12 /* interrupt priority level */ 272612Swnj #define ASTLVL 0x13 /* async. system trap level */ 282612Swnj #define SIRR 0x14 /* software interrupt request */ 292612Swnj #define SISR 0x15 /* software interrupt summary */ 302612Swnj #define ICCS 0x18 /* interval clock control */ 312612Swnj #define NICR 0x19 /* next interval count */ 322612Swnj #define ICR 0x1a /* interval count */ 332612Swnj #define TODR 0x1b /* time of year (day) */ 342612Swnj #define RXCS 0x20 /* console receiver control and status */ 352612Swnj #define RXDB 0x21 /* console receiver data buffer */ 362612Swnj #define TXCS 0x22 /* console transmitter control and status */ 372612Swnj #define TXDB 0x23 /* console transmitter data buffer */ 382612Swnj #define MAPEN 0x38 /* memory management enable */ 392612Swnj #define TBIA 0x39 /* translation buffer invalidate all */ 402612Swnj #define TBIS 0x3a /* translation buffer invalidate single */ 412612Swnj #define PMR 0x3d /* performance monitor enable */ 422612Swnj #define SID 0x3e /* system identification */ 4362Sbill 4413864Ssam #if defined(VAX780) 452612Swnj #define ACCS 0x28 /* accelerator control and status */ 462612Swnj #define ACCR 0x29 /* accelerator maintenance */ 472612Swnj #define WCSA 0x2c /* WCS address */ 482612Swnj #define WCSD 0x2d /* WCS data */ 492612Swnj #define SBIFS 0x30 /* SBI fault and status */ 502612Swnj #define SBIS 0x31 /* SBI silo */ 512612Swnj #define SBISC 0x32 /* SBI silo comparator */ 522612Swnj #define SBIMT 0x33 /* SBI maintenance */ 532612Swnj #define SBIER 0x34 /* SBI error register */ 542612Swnj #define SBITA 0x35 /* SBI timeout address */ 552612Swnj #define SBIQC 0x36 /* SBI quadword clear */ 562612Swnj #define MBRK 0x3c /* micro-program breakpoint */ 571907Swnj #endif 581907Swnj 5913864Ssam #if defined(VAX750) || defined(VAX730) 602612Swnj #define MCSR 0x17 /* machine check status register */ 611907Swnj #define CSRS 0x1c /* console storage receive status register */ 621907Swnj #define CSRD 0x1d /* console storage receive data register */ 631907Swnj #define CSTS 0x1e /* console storage transmit status register */ 641907Swnj #define CSTD 0x1f /* console storage transmit data register */ 651907Swnj #define TBDR 0x24 /* translation buffer disable register */ 661907Swnj #define CADR 0x25 /* cache disable register */ 671907Swnj #define MCESR 0x26 /* machine check error summary register */ 681907Swnj #define CAER 0x27 /* cache error */ 691907Swnj #define IUR 0x37 /* init unibus register */ 701907Swnj #define TB 0x3b /* translation buffer */ 711907Swnj #endif 72