1*1907Swnj /* mtpr.h 4.2 12/17/80 */ 262Sbill 362Sbill /* 462Sbill * VAX processor register numbers 562Sbill */ 662Sbill 762Sbill #define KSP 0 /* kernel stack pointer */ 862Sbill #define ESP 1 /* exec stack pointer */ 962Sbill #define SSP 2 /* supervisor stack pointer */ 1062Sbill #define USP 3 /* user stack pointer */ 1162Sbill #define ISP 4 /* interrupt stack pointer */ 1262Sbill #define P0BR 8 /* p0 base register */ 1362Sbill #define P0LR 9 /* p0 length register */ 1462Sbill #define P1BR 10 /* p1 base register */ 1562Sbill #define P1LR 11 /* p1 length register */ 1662Sbill #define SBR 12 /* system segment base register */ 1762Sbill #define SLR 13 /* system segment length register */ 1862Sbill #define PCBB 16 /* process control block base */ 1962Sbill #define SCBB 17 /* system control block base */ 2062Sbill #define IPL 18 /* interrupt priority level */ 2162Sbill #define ASTLVL 19 /* async. system trap level */ 2262Sbill #define SIRR 20 /* software interrupt request */ 2362Sbill #define SISR 21 /* software interrupt summary */ 2462Sbill #define ICCS 24 /* interval clock control */ 2562Sbill #define NICR 25 /* next interval count */ 2662Sbill #define ICR 26 /* interval count */ 2762Sbill #define TODR 27 /* time of year (day) */ 2862Sbill #define RXCS 32 /* console receiver control and status */ 2962Sbill #define RXDB 33 /* console receiver data buffer */ 3062Sbill #define TXCS 34 /* console transmitter control and status */ 3162Sbill #define TXDB 35 /* console transmitter data buffer */ 3262Sbill #define MAPEN 56 /* memory management enable */ 3362Sbill #define TBIA 57 /* translation buffer invalidate all */ 3462Sbill #define TBIS 58 /* translation buffer invalidate single */ 3562Sbill #define PMR 61 /* performance monitor enable */ 3662Sbill #define SID 62 /* system identification */ 3762Sbill 38*1907Swnj #if VAX==780 3962Sbill #define ACCS 40 /* accelerator control and status */ 4062Sbill #define ACCR 41 /* accelerator maintenance */ 4162Sbill #define WCSA 44 /* WCS address */ 4262Sbill #define WCSD 45 /* WCS data */ 4362Sbill #define SBIFS 48 /* SBI fault and status */ 4462Sbill #define SBIS 49 /* SBI silo */ 4562Sbill #define SBISC 50 /* SBI silo comparator */ 4662Sbill #define SBIMT 51 /* SBI maintenance */ 4762Sbill #define SBIER 52 /* SBI error register */ 4862Sbill #define SBITA 53 /* SBI timeout address */ 4962Sbill #define SBIQC 54 /* SBI quadword clear */ 5062Sbill #define MBRK 60 /* micro-program breakpoint */ 51*1907Swnj #endif 52*1907Swnj 53*1907Swnj #if VAX==750 54*1907Swnj #define CSRS 0x1c /* console storage receive status register */ 55*1907Swnj #define CSRD 0x1d /* console storage receive data register */ 56*1907Swnj #define CSTS 0x1e /* console storage transmit status register */ 57*1907Swnj #define CSTD 0x1f /* console storage transmit data register */ 58*1907Swnj #define TBDR 0x24 /* translation buffer disable register */ 59*1907Swnj #define CADR 0x25 /* cache disable register */ 60*1907Swnj #define MCESR 0x26 /* machine check error summary register */ 61*1907Swnj #define CAER 0x27 /* cache error */ 62*1907Swnj #define IUR 0x37 /* init unibus register */ 63*1907Swnj #define TB 0x3b /* translation buffer */ 64*1907Swnj #endif 65