xref: /csrg-svn/sys/vax/if/if_qereg.h (revision 44563)
135326Sbostic /*
235326Sbostic  * Copyright (c) 1988 Regents of the University of California.
335326Sbostic  * All rights reserved.
435326Sbostic  *
535326Sbostic  * This code is derived from software contributed to Berkeley by
635326Sbostic  * Digital Equipment Corp.
735326Sbostic  *
8*44563Sbostic  * %sccs.include.redist.c%
935326Sbostic  *
10*44563Sbostic  *	@(#)if_qereg.h	7.3 (Berkeley) 06/28/90
1135326Sbostic  */
1227478Skjd 
1327478Skjd /* @(#)if_qereg.h	1.2 (ULTRIX) 1/3/85 */
1427478Skjd 
1527478Skjd /****************************************************************
1627478Skjd  *								*
1727478Skjd  *        Licensed from Digital Equipment Corporation 		*
1827478Skjd  *                       Copyright (c) 				*
1927478Skjd  *               Digital Equipment Corporation			*
2027478Skjd  *                   Maynard, Massachusetts 			*
2127478Skjd  *                         1985, 1986 				*
2227478Skjd  *                    All rights reserved. 			*
2327478Skjd  *								*
2427478Skjd  *        The Information in this software is subject to change *
2527478Skjd  *   without notice and should not be construed as a commitment *
2627478Skjd  *   by  Digital  Equipment  Corporation.   Digital   makes  no *
2727478Skjd  *   representations about the suitability of this software for *
2827478Skjd  *   any purpose.  It is supplied "As Is" without expressed  or *
2927478Skjd  *   implied  warranty. 					*
3027478Skjd  *								*
3127478Skjd  *        If the Regents of the University of California or its *
3227478Skjd  *   licensees modify the software in a manner creating  	*
3327478Skjd  *   diriviative copyright rights, appropriate copyright  	*
3427478Skjd  *   legends may be placed on  the drivative work in addition   *
3527478Skjd  *   to that set forth above. 					*
3627478Skjd  *								*
3727478Skjd  ****************************************************************/
3827478Skjd /* ---------------------------------------------------------------------
3927478Skjd  * Modification History
4027478Skjd  *
4127478Skjd  *  13 Feb. 84 -- rjl
4227478Skjd  *
4327478Skjd  *	Initial version of driver. derived from IL driver.
4427478Skjd  *
4527478Skjd  * ---------------------------------------------------------------------
4627478Skjd  */
4727478Skjd 
4827478Skjd /*
4927478Skjd  * Digital Q-BUS to NI Adapter
5027478Skjd  */
5127478Skjd struct qedevice {
5227478Skjd 	u_short	qe_sta_addr[2]; 	/* Station address (actually 6 	*/
5327916Skarels 	u_short	qe_rcvlist_lo; 		/* Receive list lo address 	*/
5427916Skarels 	u_short	qe_rcvlist_hi; 		/* Receive list hi address 	*/
5527478Skjd 	u_short	qe_xmtlist_lo;		/* Transmit list lo address 	*/
5627478Skjd 	u_short	qe_xmtlist_hi;		/* Transmit list hi address 	*/
5727478Skjd 	u_short	qe_vector;		/* Interrupt vector 		*/
5827478Skjd 	u_short	qe_csr;			/* Command and Status Register 	*/
5927478Skjd };
6027478Skjd 
6127478Skjd /*
6227478Skjd  * Command and status bits (csr)
6327478Skjd  */
6427478Skjd #define QE_RCV_ENABLE	0x0001		/* Receiver enable		*/
6527478Skjd #define QE_RESET	0x0002		/* Software reset		*/
6627478Skjd #define QE_NEX_MEM_INT	0x0004		/* Non existant mem interrupt	*/
6727478Skjd #define QE_LOAD_ROM	0x0008		/* Load boot/diag from rom	*/
6827478Skjd #define QE_XL_INVALID	0x0010		/* Transmit list invalid	*/
6927478Skjd #define QE_RL_INVALID	0x0020		/* Receive list invalid		*/
7027478Skjd #define QE_INT_ENABLE	0x0040		/* Interrupt enable		*/
7127478Skjd #define QE_XMIT_INT	0x0080		/* Transmit interrupt		*/
7227478Skjd #define QE_ILOOP 	0x0100		/* Internal loopback		*/
7327478Skjd #define QE_ELOOP	0x0200		/* External loopback		*/
7427478Skjd #define QE_STIM_ENABLE	0x0400		/* Sanity timer enable		*/
7527478Skjd #define QE_POWERUP	0x1000		/* Tranceiver power on		*/
7627478Skjd #define QE_CARRIER	0x2000		/* Carrier detect		*/
7727478Skjd #define QE_RCV_INT	0x8000		/* Receiver interrupt		*/
7827478Skjd 
7927478Skjd /*
8027478Skjd  * Transmit and receive ring discriptor ---------------------------
8127478Skjd  *
8227478Skjd  * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore
8327478Skjd  * mechinism.
8427478Skjd  *
8527478Skjd  * The flag word is written on ( bits 15,15 set to 1 ) when it reads the
8627478Skjd  * descriptor. If the valid bit is set it considers the address to be valid.
8727478Skjd  * When it uses the buffer pointed to by the valid address it sets status word
8827478Skjd  * one.
8927478Skjd  */
9027478Skjd struct qe_ring	{
9127478Skjd 	u_short qe_flag;		/* Buffer utilization flags	*/
9227478Skjd 	u_short qe_addr_hi:6,		/* Hi order bits of buffer addr	*/
9327478Skjd 	      qe_odd_begin:1,		/* Odd byte begin and end (xmit)*/
9427478Skjd 	      qe_odd_end:1,
9527478Skjd 	      qe_fill1:4,
9627478Skjd 	      qe_setup:1,		/* Setup packet			*/
9727478Skjd 	      qe_eomsg:1,		/* End of message flag		*/
9827478Skjd 	      qe_chain:1,		/* Chain address instead of buf */
9927478Skjd 	      qe_valid:1;		/* Address field is valid	*/
10027478Skjd 	u_short qe_addr_lo;		/* Low order bits of address	*/
10127478Skjd 	short qe_buf_len;		/* Negative buffer length	*/
10227478Skjd 	u_short qe_status1;		/* Status word one		*/
10327478Skjd 	u_short qe_status2;		/* Status word two		*/
10427478Skjd };
10527478Skjd 
10627478Skjd /*
10727478Skjd  * Status word definations (receive)
10827478Skjd  *	word1
10927478Skjd  */
11027478Skjd #define QE_OVF			0x0001	/* Receiver overflow		*/
11127478Skjd #define QE_CRCERR		0x0002	/* CRC error			*/
11227478Skjd #define QE_FRAME		0x0004	/* Framing alignment error	*/
11327478Skjd #define QE_SHORT		0x0008	/* Packet size < 10 bytes	*/
11427478Skjd #define QE_RBL_HI		0x0700	/* Hi bits of receive len	*/
11527478Skjd #define QE_RUNT			0x0800	/* Runt packet			*/
11627478Skjd #define QE_DISCARD		0x1000	/* Discard the packet		*/
11727478Skjd #define QE_ESETUP		0x2000	/* Looped back setup or eloop	*/
11827478Skjd #define QE_ERROR		0x4000	/* Receiver error		*/
11927478Skjd #define QE_LASTNOT		0x8000	/* Not the last in the packet	*/
12027478Skjd /*	word2								*/
12127478Skjd #define QE_RBL_LO		0x00ff	/* Low bits of receive len	*/
12227478Skjd 
12327478Skjd /*
12427478Skjd  * Status word definations (transmit)
12527478Skjd  *	word1
12627478Skjd  */
12727478Skjd #define QE_CCNT			0x00f0	/* Collision count this packet	*/
12827478Skjd #define QE_FAIL			0x0100	/* Heart beat check failure	*/
12927478Skjd #define QE_ABORT		0x0200	/* Transmission abort		*/
13027478Skjd #define QE_STE16		0x0400	/* Sanity timer default on	*/
13127478Skjd #define QE_NOCAR		0x0800	/* No carrier			*/
13227478Skjd #define QE_LOSS			0x1000	/* Loss of carrier while xmit	*/
13327478Skjd /*	word2								*/
13427478Skjd #define QE_TDR			0x3fff	/* Time domain reflectometry	*/
13527478Skjd 
13627478Skjd /*
13727478Skjd  * General constant definations
13827478Skjd  */
13927478Skjd #define QEALLOC 		0	/* Allocate an mbuf		*/
14027478Skjd #define QENOALLOC		1	/* No mbuf allocation		*/
14127478Skjd #define QEDEALLOC		2	/* Release an mbuf chain	*/
14227478Skjd 
14327478Skjd #define QE_NOTYET		0x8000	/* Descriptor not in use yet	*/
14427478Skjd #define QE_INUSE		0x4000	/* Descriptor being used by QNA	*/
14527478Skjd #define QE_MASK			0xc000	/* Lastnot/error/used mask	*/
146