1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Digital Equipment Corp. 7 * 8 * Redistribution and use in source and binary forms are permitted 9 * provided that the above copyright notice and this paragraph are 10 * duplicated in all such forms and that any documentation, 11 * advertising materials, and other materials related to such 12 * distribution and use acknowledge that the software was developed 13 * by the University of California, Berkeley. The name of the 14 * University may not be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 18 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 19 * 20 * @(#)if_qe.c 7.15 (Berkeley) 06/20/90 21 */ 22 23 /* from @(#)if_qe.c 1.15 (ULTRIX) 4/16/86 */ 24 25 /**************************************************************** 26 * * 27 * Licensed from Digital Equipment Corporation * 28 * Copyright (c) * 29 * Digital Equipment Corporation * 30 * Maynard, Massachusetts * 31 * 1985, 1986 * 32 * All rights reserved. * 33 * * 34 * The Information in this software is subject to change * 35 * without notice and should not be construed as a commitment * 36 * by Digital Equipment Corporation. Digital makes no * 37 * representations about the suitability of this software for * 38 * any purpose. It is supplied "As Is" without expressed or * 39 * implied warranty. * 40 * * 41 * If the Regents of the University of California or its * 42 * licensees modify the software in a manner creating * 43 * derivative copyright rights, appropriate copyright * 44 * legends may be placed on the derivative work in addition * 45 * to that set forth above. * 46 * * 47 ****************************************************************/ 48 /* --------------------------------------------------------------------- 49 * Modification History 50 * 51 * 15-Apr-86 -- afd 52 * Rename "unused_multi" to "qunused_multi" for extending Generic 53 * kernel to MicroVAXen. 54 * 55 * 18-mar-86 -- jaw br/cvec changed to NOT use registers. 56 * 57 * 12 March 86 -- Jeff Chase 58 * Modified to handle the new MCLGET macro 59 * Changed if_qe_data.c to use more receive buffers 60 * Added a flag to poke with adb to log qe_restarts on console 61 * 62 * 19 Oct 85 -- rjl 63 * Changed the watch dog timer from 30 seconds to 3. VMS is using 64 * less than 1 second in their's. Also turned the printf into an 65 * mprintf. 66 * 67 * 09/16/85 -- Larry Cohen 68 * Add 43bsd alpha tape changes for subnet routing 69 * 70 * 1 Aug 85 -- rjl 71 * Panic on a non-existent memory interrupt and the case where a packet 72 * was chained. The first should never happen because non-existant 73 * memory interrupts cause a bus reset. The second should never happen 74 * because we hang 2k input buffers on the device. 75 * 76 * 1 Aug 85 -- rich 77 * Fixed the broadcast loopback code to handle Clusters without 78 * wedging the system. 79 * 80 * 27 Feb. 85 -- ejf 81 * Return default hardware address on ioctl request. 82 * 83 * 12 Feb. 85 -- ejf 84 * Added internal extended loopback capability. 85 * 86 * 27 Dec. 84 -- rjl 87 * Fixed bug that caused every other transmit descriptor to be used 88 * instead of every descriptor. 89 * 90 * 21 Dec. 84 -- rjl 91 * Added watchdog timer to mask hardware bug that causes device lockup. 92 * 93 * 18 Dec. 84 -- rjl 94 * Reworked driver to use q-bus mapping routines. MicroVAX-I now does 95 * copying instead of m-buf shuffleing. 96 * A number of deficencies in the hardware/firmware were compensated 97 * for. See comments in qestart and qerint. 98 * 99 * 14 Nov. 84 -- jf 100 * Added usage counts for multicast addresses. 101 * Updated general protocol support to allow access to the Ethernet 102 * header. 103 * 104 * 04 Oct. 84 -- jf 105 * Added support for new ioctls to add and delete multicast addresses 106 * and set the physical address. 107 * Add support for general protocols. 108 * 109 * 14 Aug. 84 -- rjl 110 * Integrated Shannon changes. (allow arp above 1024 and ? ) 111 * 112 * 13 Feb. 84 -- rjl 113 * 114 * Initial version of driver. derived from IL driver. 115 * 116 * --------------------------------------------------------------------- 117 */ 118 119 #include "qe.h" 120 #if NQE > 0 121 /* 122 * Digital Q-BUS to NI Adapter 123 */ 124 #include "param.h" 125 #include "systm.h" 126 #include "mbuf.h" 127 #include "buf.h" 128 #include "protosw.h" 129 #include "socket.h" 130 #include "vmmac.h" 131 #include "ioctl.h" 132 #include "errno.h" 133 #include "syslog.h" 134 #include "time.h" 135 #include "kernel.h" 136 137 #include "../net/if.h" 138 #include "../net/netisr.h" 139 #include "../net/route.h" 140 141 #ifdef INET 142 #include "../netinet/in.h" 143 #include "../netinet/in_systm.h" 144 #include "../netinet/in_var.h" 145 #include "../netinet/ip.h" 146 #include "../netinet/if_ether.h" 147 #endif 148 149 #ifdef NS 150 #include "../netns/ns.h" 151 #include "../netns/ns_if.h" 152 #endif 153 154 #ifdef ISO 155 #include "../netiso/iso.h" 156 #include "../netiso/iso_var.h" 157 extern char all_es_snpa[], all_is_snpa[]; 158 #endif 159 160 #include "../vax/pte.h" 161 #include "../vax/cpu.h" 162 #include "../vax/mtpr.h" 163 #include "if_qereg.h" 164 #include "if_uba.h" 165 #include "../vaxuba/ubareg.h" 166 #include "../vaxuba/ubavar.h" 167 168 #if NQE == 1 && !defined(QNIVERT) 169 #define NRCV 15 /* Receive descriptors */ 170 #else 171 #define NRCV 10 /* Receive descriptors */ 172 #endif 173 #define NXMT 5 /* Transmit descriptors */ 174 #define NTOT (NXMT + NRCV) 175 176 #define QETIMEOUT 2 /* transmit timeout, must be > 1 */ 177 #define QESLOWTIMEOUT 40 /* timeout when no xmits in progress */ 178 179 /* 180 * This constant should really be 60 because the qna adds 4 bytes of crc. 181 * However when set to 60 our packets are ignored by deuna's , 3coms are 182 * okay ?????????????????????????????????????????? 183 */ 184 #define MINDATA 64 185 186 /* 187 * Ethernet software status per interface. 188 * 189 * Each interface is referenced by a network interface structure, 190 * qe_if, which the routing code uses to locate the interface. 191 * This structure contains the output queue for the interface, its address, ... 192 */ 193 struct qe_softc { 194 struct arpcom qe_ac; /* Ethernet common part */ 195 #define qe_if qe_ac.ac_if /* network-visible interface */ 196 #define qe_addr qe_ac.ac_enaddr /* hardware Ethernet address */ 197 struct ifubinfo qe_uba; /* Q-bus resources */ 198 struct ifrw qe_ifr[NRCV]; /* for receive buffers; */ 199 struct ifxmt qe_ifw[NXMT]; /* for xmit buffers; */ 200 int qe_flags; /* software state */ 201 #define QEF_RUNNING 0x01 202 #define QEF_SETADDR 0x02 203 #define QEF_FASTTIMEO 0x04 204 int setupaddr; /* mapping info for setup pkts */ 205 int ipl; /* interrupt priority */ 206 struct qe_ring *rringaddr; /* mapping info for rings */ 207 struct qe_ring *tringaddr; /* "" */ 208 struct qe_ring rring[NRCV+1]; /* Receive ring descriptors */ 209 struct qe_ring tring[NXMT+1]; /* Transmit ring descriptors */ 210 u_char setup_pkt[16][8]; /* Setup packet */ 211 int rindex; /* Receive index */ 212 int tindex; /* Transmit index */ 213 int otindex; /* Old transmit index */ 214 int qe_intvec; /* Interrupt vector */ 215 struct qedevice *addr; /* device addr */ 216 int setupqueued; /* setup packet queued */ 217 int nxmit; /* Transmits in progress */ 218 int qe_restarts; /* timeouts */ 219 } qe_softc[NQE]; 220 221 struct uba_device *qeinfo[NQE]; 222 223 extern struct timeval time; 224 225 int qeprobe(), qeattach(), qeintr(), qetimeout(); 226 int qeinit(), qeioctl(), qereset(), qestart(); 227 228 u_short qestd[] = { 0 }; 229 struct uba_driver qedriver = 230 { qeprobe, 0, qeattach, 0, qestd, "qe", qeinfo }; 231 232 #define QEUNIT(x) minor(x) 233 /* 234 * The deqna shouldn't receive more than ETHERMTU + sizeof(struct ether_header) 235 * but will actually take in up to 2048 bytes. To guard against the receiver 236 * chaining buffers (which we aren't prepared to handle) we allocate 2kb 237 * size buffers. 238 */ 239 #define MAXPACKETSIZE 2048 /* Should really be ETHERMTU */ 240 /* 241 * Probe the QNA to see if it's there 242 */ 243 qeprobe(reg, ui) 244 caddr_t reg; 245 struct uba_device *ui; 246 { 247 register int br, cvec; /* r11, r10 value-result */ 248 register struct qedevice *addr = (struct qedevice *)reg; 249 register struct qe_ring *rp; 250 register struct qe_ring *prp; /* physical rp */ 251 register int i; 252 register struct qe_softc *sc = &qe_softc[ui->ui_unit]; 253 254 #ifdef lint 255 br = 0; cvec = br; br = cvec; 256 qeintr(0); 257 #endif 258 259 /* 260 * The QNA interrupts on i/o operations. To do an I/O operation 261 * we have to setup the interface by transmitting a setup packet. 262 */ 263 addr->qe_csr = QE_RESET; 264 addr->qe_csr &= ~QE_RESET; 265 addr->qe_vector = (uba_hd[numuba].uh_lastiv -= 4); 266 267 /* 268 * Map the communications area and the setup packet. 269 */ 270 sc->setupaddr = 271 uballoc(0, (caddr_t)sc->setup_pkt, sizeof(sc->setup_pkt), 0); 272 sc->rringaddr = (struct qe_ring *) uballoc(0, (caddr_t)sc->rring, 273 sizeof(struct qe_ring) * (NTOT+2), 0); 274 prp = (struct qe_ring *)UBAI_ADDR((int)sc->rringaddr); 275 276 /* 277 * The QNA will loop the setup packet back to the receive ring 278 * for verification, therefore we initialize the first 279 * receive & transmit ring descriptors and link the setup packet 280 * to them. 281 */ 282 qeinitdesc(sc->tring, (caddr_t)UBAI_ADDR(sc->setupaddr), 283 sizeof(sc->setup_pkt)); 284 qeinitdesc(sc->rring, (caddr_t)UBAI_ADDR(sc->setupaddr), 285 sizeof(sc->setup_pkt)); 286 287 rp = (struct qe_ring *)sc->tring; 288 rp->qe_setup = 1; 289 rp->qe_eomsg = 1; 290 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 291 rp->qe_valid = 1; 292 293 rp = (struct qe_ring *)sc->rring; 294 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 295 rp->qe_valid = 1; 296 297 /* 298 * Get the addr off of the interface and place it into the setup 299 * packet. This code looks strange due to the fact that the address 300 * is placed in the setup packet in col. major order. 301 */ 302 for( i = 0 ; i < 6 ; i++ ) 303 sc->setup_pkt[i][1] = addr->qe_sta_addr[i]; 304 305 qesetup( sc ); 306 /* 307 * Start the interface and wait for the packet. 308 */ 309 (void) spl6(); 310 addr->qe_csr = QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT; 311 addr->qe_rcvlist_lo = (short)prp; 312 addr->qe_rcvlist_hi = (short)((int)prp >> 16); 313 prp += NRCV+1; 314 addr->qe_xmtlist_lo = (short)prp; 315 addr->qe_xmtlist_hi = (short)((int)prp >> 16); 316 DELAY(10000); 317 /* 318 * All done with the bus resources. 319 */ 320 ubarelse(0, &sc->setupaddr); 321 ubarelse(0, (int *)&sc->rringaddr); 322 sc->ipl = br = qbgetpri(); 323 return( sizeof(struct qedevice) ); 324 } 325 326 /* 327 * Interface exists: make available by filling in network interface 328 * record. System will initialize the interface when it is ready 329 * to accept packets. 330 */ 331 qeattach(ui) 332 struct uba_device *ui; 333 { 334 register struct qe_softc *sc = &qe_softc[ui->ui_unit]; 335 register struct ifnet *ifp = &sc->qe_if; 336 register struct qedevice *addr = (struct qedevice *)ui->ui_addr; 337 register int i; 338 339 ifp->if_unit = ui->ui_unit; 340 ifp->if_name = "qe"; 341 ifp->if_mtu = ETHERMTU; 342 ifp->if_flags = IFF_BROADCAST; 343 344 /* 345 * Read the address from the prom and save it. 346 */ 347 for( i=0 ; i<6 ; i++ ) 348 sc->setup_pkt[i][1] = sc->qe_addr[i] = addr->qe_sta_addr[i] & 0xff; 349 addr->qe_vector |= 1; 350 printf("qe%d: %s, hardware address %s\n", ui->ui_unit, 351 addr->qe_vector&01 ? "delqa":"deqna", 352 ether_sprintf(sc->qe_addr)); 353 addr->qe_vector &= ~1; 354 355 /* 356 * Save the vector for initialization at reset time. 357 */ 358 sc->qe_intvec = addr->qe_vector; 359 360 ifp->if_init = qeinit; 361 ifp->if_output = ether_output; 362 ifp->if_start = qestart; 363 ifp->if_ioctl = qeioctl; 364 ifp->if_reset = qereset; 365 ifp->if_watchdog = qetimeout; 366 sc->qe_uba.iff_flags = UBA_CANTWAIT; 367 if_attach(ifp); 368 } 369 370 /* 371 * Reset of interface after UNIBUS reset. 372 * If interface is on specified uba, reset its state. 373 */ 374 qereset(unit, uban) 375 int unit, uban; 376 { 377 register struct uba_device *ui; 378 379 if (unit >= NQE || (ui = qeinfo[unit]) == 0 || ui->ui_alive == 0 || 380 ui->ui_ubanum != uban) 381 return; 382 printf(" qe%d", unit); 383 qe_softc[unit].qe_if.if_flags &= ~IFF_RUNNING; 384 qeinit(unit); 385 } 386 387 /* 388 * Initialization of interface. 389 */ 390 qeinit(unit) 391 int unit; 392 { 393 register struct qe_softc *sc = &qe_softc[unit]; 394 register struct uba_device *ui = qeinfo[unit]; 395 register struct qedevice *addr = (struct qedevice *)ui->ui_addr; 396 register struct ifnet *ifp = &sc->qe_if; 397 register i; 398 int s; 399 400 /* address not known */ 401 if (ifp->if_addrlist == (struct ifaddr *)0) 402 return; 403 if (sc->qe_flags & QEF_RUNNING) 404 return; 405 406 if ((ifp->if_flags & IFF_RUNNING) == 0) { 407 /* 408 * map the communications area onto the device 409 */ 410 i = uballoc(0, (caddr_t)sc->rring, 411 sizeof(struct qe_ring) * (NTOT+2), 0); 412 if (i == 0) 413 goto fail; 414 sc->rringaddr = (struct qe_ring *)UBAI_ADDR(i); 415 sc->tringaddr = sc->rringaddr + NRCV + 1; 416 i = uballoc(0, (caddr_t)sc->setup_pkt, 417 sizeof(sc->setup_pkt), 0); 418 if (i == 0) 419 goto fail; 420 sc->setupaddr = UBAI_ADDR(i); 421 /* 422 * init buffers and maps 423 */ 424 if (if_ubaminit(&sc->qe_uba, ui->ui_ubanum, 425 sizeof (struct ether_header), (int)btoc(MAXPACKETSIZE), 426 sc->qe_ifr, NRCV, sc->qe_ifw, NXMT) == 0) { 427 fail: 428 printf("qe%d: can't allocate uba resources\n", unit); 429 sc->qe_if.if_flags &= ~IFF_UP; 430 return; 431 } 432 } 433 /* 434 * Init the buffer descriptors and indexes for each of the lists and 435 * loop them back to form a ring. 436 */ 437 for (i = 0; i < NRCV; i++) { 438 qeinitdesc( &sc->rring[i], 439 (caddr_t)UBAI_ADDR(sc->qe_ifr[i].ifrw_info), MAXPACKETSIZE); 440 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET; 441 sc->rring[i].qe_valid = 1; 442 } 443 qeinitdesc(&sc->rring[i], (caddr_t)NULL, 0); 444 445 sc->rring[i].qe_addr_lo = (short)sc->rringaddr; 446 sc->rring[i].qe_addr_hi = (short)((int)sc->rringaddr >> 16); 447 sc->rring[i].qe_chain = 1; 448 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET; 449 sc->rring[i].qe_valid = 1; 450 451 for( i = 0 ; i <= NXMT ; i++ ) 452 qeinitdesc(&sc->tring[i], (caddr_t)NULL, 0); 453 i--; 454 455 sc->tring[i].qe_addr_lo = (short)sc->tringaddr; 456 sc->tring[i].qe_addr_hi = (short)((int)sc->tringaddr >> 16); 457 sc->tring[i].qe_chain = 1; 458 sc->tring[i].qe_flag = sc->tring[i].qe_status1 = QE_NOTYET; 459 sc->tring[i].qe_valid = 1; 460 461 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0; 462 463 /* 464 * Take the interface out of reset, program the vector, 465 * enable interrupts, and tell the world we are up. 466 */ 467 s = splimp(); 468 addr->qe_vector = sc->qe_intvec; 469 sc->addr = addr; 470 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 471 QE_RCV_INT | QE_ILOOP; 472 addr->qe_rcvlist_lo = (short)sc->rringaddr; 473 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16); 474 ifp->if_flags |= IFF_UP | IFF_RUNNING; 475 sc->qe_flags |= QEF_RUNNING; 476 qesetup( sc ); 477 (void) qestart( ifp ); 478 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Start watchdog */ 479 splx( s ); 480 } 481 482 /* 483 * Start output on interface. 484 * 485 */ 486 qestart(ifp) 487 struct ifnet *ifp; 488 { 489 int unit = ifp->if_unit; 490 struct uba_device *ui = qeinfo[unit]; 491 register struct qe_softc *sc = &qe_softc[unit]; 492 register struct qedevice *addr; 493 register struct qe_ring *rp; 494 register index; 495 struct mbuf *m; 496 int buf_addr, len, s; 497 498 499 s = splimp(); 500 addr = (struct qedevice *)ui->ui_addr; 501 /* 502 * The deqna doesn't look at anything but the valid bit 503 * to determine if it should transmit this packet. If you have 504 * a ring and fill it the device will loop indefinately on the 505 * packet and continue to flood the net with packets until you 506 * break the ring. For this reason we never queue more than n-1 507 * packets in the transmit ring. 508 * 509 * The microcoders should have obeyed their own defination of the 510 * flag and status words, but instead we have to compensate. 511 */ 512 for( index = sc->tindex; 513 sc->tring[index].qe_valid == 0 && sc->nxmit < (NXMT-1) ; 514 sc->tindex = index = ++index % NXMT){ 515 rp = &sc->tring[index]; 516 if( sc->setupqueued ) { 517 buf_addr = sc->setupaddr; 518 len = 128; 519 rp->qe_setup = 1; 520 sc->setupqueued = 0; 521 } else { 522 IF_DEQUEUE(&sc->qe_if.if_snd, m); 523 if( m == 0 ){ 524 splx(s); 525 return (0); 526 } 527 buf_addr = sc->qe_ifw[index].ifw_info; 528 len = if_ubaput(&sc->qe_uba, &sc->qe_ifw[index], m); 529 } 530 /* 531 * Does buffer end on odd byte ? 532 */ 533 if( len & 1 ) { 534 len++; 535 rp->qe_odd_end = 1; 536 } 537 if( len < MINDATA ) 538 len = MINDATA; 539 rp->qe_buf_len = -(len/2); 540 buf_addr = UBAI_ADDR(buf_addr); 541 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 542 rp->qe_addr_lo = (short)buf_addr; 543 rp->qe_addr_hi = (short)(buf_addr >> 16); 544 rp->qe_eomsg = 1; 545 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 546 rp->qe_valid = 1; 547 if (sc->nxmit++ == 0) { 548 sc->qe_flags |= QEF_FASTTIMEO; 549 sc->qe_if.if_timer = QETIMEOUT; 550 } 551 552 /* 553 * See if the xmit list is invalid. 554 */ 555 if( addr->qe_csr & QE_XL_INVALID ) { 556 buf_addr = (int)(sc->tringaddr+index); 557 addr->qe_xmtlist_lo = (short)buf_addr; 558 addr->qe_xmtlist_hi = (short)(buf_addr >> 16); 559 } 560 } 561 splx( s ); 562 return (0); 563 } 564 565 /* 566 * Ethernet interface interrupt processor 567 */ 568 qeintr(unit) 569 int unit; 570 { 571 register struct qe_softc *sc = &qe_softc[unit]; 572 struct qedevice *addr = (struct qedevice *)qeinfo[unit]->ui_addr; 573 int buf_addr, csr; 574 575 #ifdef notdef 576 splx(sc->ipl); 577 #else 578 (void) splimp(); 579 #endif 580 if (!(sc->qe_flags & QEF_FASTTIMEO)) 581 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Restart timer clock */ 582 csr = addr->qe_csr; 583 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT | QE_ILOOP; 584 if( csr & QE_RCV_INT ) 585 qerint( unit ); 586 if( csr & QE_XMIT_INT ) 587 qetint( unit ); 588 if( csr & QE_NEX_MEM_INT ) 589 printf("qe%d: Nonexistent memory interrupt\n", unit); 590 591 if( addr->qe_csr & QE_RL_INVALID && sc->rring[sc->rindex].qe_status1 == QE_NOTYET ) { 592 buf_addr = (int)&sc->rringaddr[sc->rindex]; 593 addr->qe_rcvlist_lo = (short)buf_addr; 594 addr->qe_rcvlist_hi = (short)(buf_addr >> 16); 595 } 596 } 597 598 /* 599 * Ethernet interface transmit interrupt. 600 */ 601 602 qetint(unit) 603 int unit; 604 { 605 register struct qe_softc *sc = &qe_softc[unit]; 606 register struct qe_ring *rp; 607 register struct ifxmt *ifxp; 608 int status1, setupflag; 609 short len; 610 611 612 while( sc->otindex != sc->tindex && sc->tring[sc->otindex].qe_status1 != QE_NOTYET && sc->nxmit > 0 ) { 613 /* 614 * Save the status words from the descriptor so that it can 615 * be released. 616 */ 617 rp = &sc->tring[sc->otindex]; 618 status1 = rp->qe_status1; 619 setupflag = rp->qe_setup; 620 len = (-rp->qe_buf_len) * 2; 621 if( rp->qe_odd_end ) 622 len++; 623 /* 624 * Init the buffer descriptor 625 */ 626 bzero((caddr_t)rp, sizeof(struct qe_ring)); 627 if( --sc->nxmit == 0 ) { 628 sc->qe_flags &= ~QEF_FASTTIMEO; 629 sc->qe_if.if_timer = QESLOWTIMEOUT; 630 } 631 if( !setupflag ) { 632 /* 633 * Do some statistics. 634 */ 635 sc->qe_if.if_opackets++; 636 sc->qe_if.if_collisions += ( status1 & QE_CCNT ) >> 4; 637 if (status1 & QE_ERROR) 638 sc->qe_if.if_oerrors++; 639 /* 640 * If this was a broadcast packet loop it 641 * back because the hardware can't hear its own 642 * transmits. 643 */ 644 ifxp = &sc->qe_ifw[sc->otindex]; 645 if (bcmp((caddr_t)((struct ether_header *)ifxp->ifw_addr)->ether_dhost, 646 (caddr_t)etherbroadcastaddr, 647 sizeof(etherbroadcastaddr)) == 0) 648 qeread(sc, &ifxp->ifrw, 649 len - sizeof(struct ether_header)); 650 if (ifxp->ifw_xtofree) { 651 m_freem(ifxp->ifw_xtofree); 652 ifxp->ifw_xtofree = 0; 653 } 654 } 655 sc->otindex = ++sc->otindex % NXMT; 656 } 657 (void) qestart( &sc->qe_if ); 658 } 659 660 /* 661 * Ethernet interface receiver interrupt. 662 * If can't determine length from type, then have to drop packet. 663 * Othewise decapsulate packet based on type and pass to type specific 664 * higher-level input routine. 665 */ 666 qerint(unit) 667 int unit; 668 { 669 register struct qe_softc *sc = &qe_softc[unit]; 670 register struct qe_ring *rp; 671 int len, status1, status2; 672 int bufaddr; 673 674 /* 675 * Traverse the receive ring looking for packets to pass back. 676 * The search is complete when we find a descriptor not in use. 677 * 678 * As in the transmit case the deqna doesn't honor it's own protocols 679 * so there exists the possibility that the device can beat us around 680 * the ring. The proper way to guard against this is to insure that 681 * there is always at least one invalid descriptor. We chose instead 682 * to make the ring large enough to minimize the problem. With a ring 683 * size of 4 we haven't been able to see the problem. To be safe we 684 * doubled that to 8. 685 * 686 */ 687 for( ; sc->rring[sc->rindex].qe_status1 != QE_NOTYET ; sc->rindex = ++sc->rindex % NRCV ){ 688 rp = &sc->rring[sc->rindex]; 689 status1 = rp->qe_status1; 690 status2 = rp->qe_status2; 691 bzero((caddr_t)rp, sizeof(struct qe_ring)); 692 if( (status1 & QE_MASK) == QE_MASK ) 693 panic("qe: chained packet"); 694 len = ((status1 & QE_RBL_HI) | (status2 & QE_RBL_LO)) + 60; 695 sc->qe_if.if_ipackets++; 696 697 if (status1 & QE_ERROR) { 698 if ((status1 & QE_RUNT) == 0) 699 sc->qe_if.if_ierrors++; 700 } else { 701 /* 702 * We don't process setup packets. 703 */ 704 if( !(status1 & QE_ESETUP) ) 705 qeread(sc, &sc->qe_ifr[sc->rindex], 706 len - sizeof(struct ether_header)); 707 } 708 /* 709 * Return the buffer to the ring 710 */ 711 bufaddr = (int)UBAI_ADDR(sc->qe_ifr[sc->rindex].ifrw_info); 712 rp->qe_buf_len = -((MAXPACKETSIZE)/2); 713 rp->qe_addr_lo = (short)bufaddr; 714 rp->qe_addr_hi = (short)((int)bufaddr >> 16); 715 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 716 rp->qe_valid = 1; 717 } 718 } 719 720 /* 721 * Process an ioctl request. 722 */ 723 qeioctl(ifp, cmd, data) 724 register struct ifnet *ifp; 725 int cmd; 726 caddr_t data; 727 { 728 struct qe_softc *sc = &qe_softc[ifp->if_unit]; 729 struct ifaddr *ifa = (struct ifaddr *)data; 730 int s = splimp(), error = 0; 731 732 switch (cmd) { 733 734 case SIOCSIFADDR: 735 ifp->if_flags |= IFF_UP; 736 qeinit(ifp->if_unit); 737 switch(ifa->ifa_addr->sa_family) { 738 #ifdef INET 739 case AF_INET: 740 ((struct arpcom *)ifp)->ac_ipaddr = 741 IA_SIN(ifa)->sin_addr; 742 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr); 743 break; 744 #endif 745 #ifdef NS 746 case AF_NS: 747 { 748 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 749 750 if (ns_nullhost(*ina)) 751 ina->x_host = *(union ns_host *)(sc->qe_addr); 752 else 753 qe_setaddr(ina->x_host.c_host, ifp->if_unit); 754 break; 755 } 756 #endif 757 } 758 break; 759 760 case SIOCSIFFLAGS: 761 if ((ifp->if_flags & IFF_UP) == 0 && 762 sc->qe_flags & QEF_RUNNING) { 763 ((struct qedevice *) 764 (qeinfo[ifp->if_unit]->ui_addr))->qe_csr = QE_RESET; 765 sc->qe_flags &= ~QEF_RUNNING; 766 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == 767 IFF_RUNNING && (sc->qe_flags & QEF_RUNNING) == 0) 768 qerestart(sc); 769 break; 770 771 default: 772 error = EINVAL; 773 774 } 775 splx(s); 776 return (error); 777 } 778 779 /* 780 * set ethernet address for unit 781 */ 782 qe_setaddr(physaddr, unit) 783 u_char *physaddr; 784 int unit; 785 { 786 register struct qe_softc *sc = &qe_softc[unit]; 787 register int i; 788 789 for (i = 0; i < 6; i++) 790 sc->setup_pkt[i][1] = sc->qe_addr[i] = physaddr[i]; 791 sc->qe_flags |= QEF_SETADDR; 792 if (sc->qe_if.if_flags & IFF_RUNNING) 793 qesetup(sc); 794 qeinit(unit); 795 } 796 797 798 /* 799 * Initialize a ring descriptor with mbuf allocation side effects 800 */ 801 qeinitdesc(rp, addr, len) 802 register struct qe_ring *rp; 803 caddr_t addr; /* mapped address */ 804 int len; 805 { 806 /* 807 * clear the entire descriptor 808 */ 809 bzero((caddr_t)rp, sizeof(struct qe_ring)); 810 811 if( len ) { 812 rp->qe_buf_len = -(len/2); 813 rp->qe_addr_lo = (short)addr; 814 rp->qe_addr_hi = (short)((int)addr >> 16); 815 } 816 } 817 /* 818 * Build a setup packet - the physical address will already be present 819 * in first column. 820 */ 821 qesetup( sc ) 822 struct qe_softc *sc; 823 { 824 register i, j; 825 826 /* 827 * Copy the target address to the rest of the entries in this row. 828 */ 829 for ( j = 0; j < 6 ; j++ ) 830 for ( i = 2 ; i < 8 ; i++ ) 831 sc->setup_pkt[j][i] = sc->setup_pkt[j][1]; 832 /* 833 * Duplicate the first half. 834 */ 835 bcopy((caddr_t)sc->setup_pkt[0], (caddr_t)sc->setup_pkt[8], 64); 836 /* 837 * Fill in the broadcast (and ISO multicast) address(es). 838 */ 839 for ( i = 0; i < 6 ; i++ ) { 840 sc->setup_pkt[i][2] = 0xff; 841 #ifdef ISO 842 sc->setup_pkt[i][3] = all_es_snpa[i]; 843 sc->setup_pkt[i][4] = all_is_snpa[i]; 844 #endif 845 } 846 sc->setupqueued++; 847 } 848 849 /* 850 * Pass a packet to the higher levels. 851 * We deal with the trailer protocol here. 852 */ 853 qeread(sc, ifrw, len) 854 register struct qe_softc *sc; 855 struct ifrw *ifrw; 856 int len; 857 { 858 struct ether_header *eh; 859 struct mbuf *m; 860 int off, resid, s; 861 struct ifqueue *inq; 862 863 /* 864 * Deal with trailer protocol: if type is INET trailer 865 * get true type from first 16-bit word past data. 866 * Remember that type was trailer by setting off. 867 */ 868 869 eh = (struct ether_header *)ifrw->ifrw_addr; 870 eh->ether_type = ntohs((u_short)eh->ether_type); 871 #define qedataaddr(eh, off, type) ((type)(((caddr_t)((eh)+1)+(off)))) 872 if (eh->ether_type >= ETHERTYPE_TRAIL && 873 eh->ether_type < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 874 off = (eh->ether_type - ETHERTYPE_TRAIL) * 512; 875 if (off >= ETHERMTU) 876 return; /* sanity */ 877 eh->ether_type = ntohs(*qedataaddr(eh,off, u_short *)); 878 resid = ntohs(*(qedataaddr(eh, off+2, u_short *))); 879 if (off + resid > len) 880 return; /* sanity */ 881 len = off + resid; 882 } else 883 off = 0; 884 if (len == 0) 885 return; 886 887 /* 888 * Pull packet off interface. Off is nonzero if packet 889 * has trailing header; qeget will then force this header 890 * information to be at the front, but we still have to drop 891 * the type and length which are at the front of any trailer data. 892 */ 893 m = if_ubaget(&sc->qe_uba, ifrw, len, off, &sc->qe_if); 894 895 if (m) 896 ether_input(&sc->qe_if, eh, m); 897 } 898 899 /* 900 * Watchdog timeout routine. There is a condition in the hardware that 901 * causes the board to lock up under heavy load. This routine detects 902 * the hang up and restarts the device. 903 */ 904 qetimeout(unit) 905 int unit; 906 { 907 register struct qe_softc *sc; 908 909 sc = &qe_softc[unit]; 910 #ifdef notdef 911 log(LOG_ERR, "qe%d: transmit timeout, restarted %d\n", 912 unit, sc->qe_restarts++); 913 #endif 914 qerestart(sc); 915 } 916 /* 917 * Restart for board lockup problem. 918 */ 919 qerestart(sc) 920 register struct qe_softc *sc; 921 { 922 register struct ifnet *ifp = &sc->qe_if; 923 register struct qedevice *addr = sc->addr; 924 register struct qe_ring *rp; 925 register i; 926 927 addr->qe_csr = QE_RESET; 928 addr->qe_csr &= ~QE_RESET; 929 qesetup( sc ); 930 for (i = 0, rp = sc->tring; i < NXMT; rp++, i++) { 931 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 932 rp->qe_valid = 0; 933 } 934 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0; 935 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 936 QE_RCV_INT | QE_ILOOP; 937 addr->qe_rcvlist_lo = (short)sc->rringaddr; 938 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16); 939 sc->qe_flags |= QEF_RUNNING; 940 (void) qestart(ifp); 941 } 942 #endif 943