123301Smckusick /* 229287Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 335325Sbostic * All rights reserved. 423301Smckusick * 5*44562Sbostic * %sccs.include.redist.c% 635325Sbostic * 7*44562Sbostic * @(#)if_pclreg.h 7.3 (Berkeley) 06/28/90 823301Smckusick */ 911817Ssam 1011817Ssam /* 1111817Ssam * DEC CSS PCL-11B Parallel Communications Interface 1211817Ssam */ 1311817Ssam 1411817Ssam struct pcldevice { 1511817Ssam u_short pcl_tcr; /* Transmitter Command Register */ 1611817Ssam u_short pcl_tsr; /* Transmitter Status Register */ 1711817Ssam u_short pcl_tsdb; /* Transmitter Source Data Buffer */ 1811817Ssam short pcl_tsbc; /* Transmitter Source Byte Count */ 1911817Ssam u_short pcl_tsba; /* Transmitter Source Bus Address */ 2011817Ssam u_short pcl_tmmr; /* Transmitter Master/Maint Regs */ 2111817Ssam u_short pcl_tscrc; /* Transmitter Source CRC */ 2211817Ssam u_short pcl_spare; 2311817Ssam u_short pcl_rcr; /* Receiver Command Register */ 2411817Ssam u_short pcl_rsr; /* Receiver Status Register */ 2511817Ssam u_short pcl_rddb; /* Receiver Destination Data Buffer */ 2611817Ssam short pcl_rdbc; /* Receiver Destination Byte Count */ 2711817Ssam u_short pcl_rdba; /* Receiver Destination Bus Address */ 2811817Ssam u_short pcl_rdcrc; /* Receiver Destination CRC */ 2911817Ssam }; 3011817Ssam 3111817Ssam /* Transmitter Command and Status Bits */ 3211817Ssam #define PCL_STTXM (1<<0) /* Start transmission */ 3311817Ssam #define PCL_TXINIT (1<<1) /* Transmitter Initialize */ 3411817Ssam #define PCL_IE (1<<6) /* Interrupt Enable */ 3511817Ssam #define PCL_SNDWD (1<<13) /* Send word */ 3611817Ssam #define PCL_TXNPR (1<<14) /* Transmitter NPR */ 3711817Ssam #define PCL_RIB (1<<15) /* Retry if busy */ 3811817Ssam 3911817Ssam #define PCL_RESPA (3<<0) /* Response A bits (tsr & rsr) */ 4011817Ssam #define PCL_RESPB (3<<2) /* Response B bits (tsr & rsr) */ 4111817Ssam #define PCL_MSTDWN (1<<11) /* Master down */ 4211817Ssam #define PCL_ERR (1<<15) /* Error summary */ 4311817Ssam 4411817Ssam #define PCL_MASTER (1<<8) /* Set MASTER status */ 4511817Ssam #define PCL_AUTOADDR (1<<12) /* Auto time slicing */ 4611817Ssam 4711817Ssam /* Receiver Command and Status Bits */ 4811817Ssam #define PCL_RCVDAT (1<<0) /* Receive data */ 4911817Ssam #define PCL_RCINIT (1<<1) /* Receiver Initialize */ 5011817Ssam #define PCL_RCVWD (1<<13) /* Receive word */ 5111817Ssam #define PCL_RCNPR (1<<14) /* Receive NRP */ 5211817Ssam #define PCL_REJ (1<<15) /* Reject transmission */ 5311817Ssam 5411817Ssam #define PCL_BCOFL (1<<9) /* Byte Counter Overflow */ 5511817Ssam 5611817Ssam #define PCL_TERRBITS "\20\20ERR\17NXL\16MEM_OFL\15TXM_ERR\14MST_DWN\13TIM_OUT\12OVERRUN\11DTI_RDY\10SUC_TXF\07BUSY\06SOREJ\05TBS_BUSY" 5711817Ssam #define PCL_TCSRBITS "\20\20RIB\17TX_NPR\16SND_WD\10RD_SILO\07IE\04DTO_RDY\03INH_ADI\02TX_INIT\01START_TXM" 5811817Ssam 5911817Ssam #define PCL_RERRBITS "\20\20ERR\17NXL\16MEM_OFL\15TXM_ERR\14PARITY\13TIM_OUT\12BC_OFL\11DTO_RDY\10SUC_TXF\07BUSY\06REJ_COMP\05CHN_OPN" 6011817Ssam #define PCL_RCSRBITS "\20\20REJ\17RC_NPR\16RCV_WD\10LD_SILO\07IE\04DTI_RDY\03INH_ADI\02RC_INIT\01RCV_DAT" 61