123297Smckusick /* 2*24462Skarels * @(#)if_hyreg.h 6.4 (Berkeley) 08/28/85 323297Smckusick * 4*24462Skarels * $Header: if_hyreg.h,v 10.0 84/06/30 19:51:34 steveg Stable $ 5*24462Skarels * $Locker: $ 6*24462Skarels * 7*24462Skarels * Modifications from Berkeley 4.2 BSD 8*24462Skarels * Copyright (c) 1983, Tektronix Inc. 9*24462Skarels * All Rights Reserved 10*24462Skarels * 1123297Smckusick */ 1211194Ssam 13*24462Skarels 1411194Ssam /* 1511194Ssam * Network Systems Corporation Hyperchannel interface 1611194Ssam * 1711194Ssam * supports A410 adapter interfaced via a DEC DR-11B, NSC PI-13 or PI-14 1811194Ssam * (PI-14 is a PI-13 with different line drivers, software is 1911194Ssam * identical to a PI-13) 2011194Ssam * 2111194Ssam * Written by Steve Glaser, Tektronix Inc., July 1982 2211194Ssam * 2311194Ssam * NOTE: 2411194Ssam * 2511194Ssam * DR11B code has not been fully checked out with 4.1a. 2611194Ssam * The first adapters at Tek came with DR11Bs, and the code once worked, 2711194Ssam * but those have been upgraded to PI-13s. 2811194Ssam */ 2911194Ssam 3011194Ssam /* 3111194Ssam * The HYPERchannel driver sends and receives messages formatted: 3211194Ssam * 3311194Ssam * +---------------------------------------+ --- 3411194Ssam * | | /|\ 3511194Ssam * | HYPERchannel adapter header (hy_hdr) | | 3611194Ssam * | | | 3711194Ssam * +---------------------------------------+ | 3811194Ssam * | | | 3911194Ssam * | Internet Protocol header (ip) | message proper 4011194Ssam * | | (64 bytes max) 4111194Ssam * +---------------------------------------+ | 4211194Ssam * | | | 4311194Ssam * | TCP header + user data | | 4411194Ssam * | (if it all fits here) | | 4511194Ssam * | | \|/ 4611194Ssam * +---------------------------------------+ --- 4711194Ssam * 4811194Ssam * +---------------------------------------+ --- 4911194Ssam * | | /|\ 5011194Ssam * | | | 5111194Ssam * | TCP header + user data | associated data 5211194Ssam * | | | 5311194Ssam * | | \|/ 5411194Ssam * +---------------------------------------+ --- 5511194Ssam * 5611194Ssam * If all of the datagram will fit in the message proper (including 5711194Ssam * the TCP header and user data) the entire datagram is passed in 5811194Ssam * the message proper and the associated data feature of the HYPERchannel 5911194Ssam * is not used. 6011194Ssam * 6111194Ssam * The mapping from internet addresses to HYPERchannel addresses is: 6211194Ssam * 6311194Ssam * 0 7 8 15 16 31 6411194Ssam * +---------+---------+-----------------------+ 6511194Ssam * | network | special | HYPERchannel address | 6611194Ssam * +---------+---------+-----------------------+ 6711194Ssam * 6811194Ssam * |<------------ internet address ----------->| 6911194Ssam * 7011194Ssam * The hyperchannel address is decoded as follows: 7111194Ssam * 7211194Ssam * 0 7 8 13 14 15 7311194Ssam * +-------------------+----------------+------+ 7411194Ssam * | adapter number | zero | port | 7511194Ssam * +-------------------+----------------+------+ 7611194Ssam * 7711194Ssam * The low 2 bits are port number (interpreted by hyperchannel hardware). 7811194Ssam * 7911194Ssam * The encoding of special bits is: 8011194Ssam * 8111194Ssam * 00 normal packet 8211194Ssam * 8311194Ssam * 01 loop this packet back to the sender at the 8411194Ssam * specified adapter (ip header source/destination addresses 8511194Ssam * swapped before sending, command bits added to tell the 8611194Ssam * remote HYPERchannel adapter debug & performance studies] 8711194Ssam * this code acts like 02 (below) if the ip destination (before 8811194Ssam * any swapping) and the destination address don't match (e.g. 8911194Ssam * this packet is being routed through a gateway) 9011194Ssam * 9111194Ssam * 02 loop this packet back to the sender at the 9211194Ssam * specified adapter, but go through the specified adapter's 9311194Ssam * IP. This is for testing IP's store and forward mechanism. 9411194Ssam * 9511194Ssam * other undefined, currently treated as normal packet 9611194Ssam * 9711194Ssam */ 9811194Ssam #define MPSIZE 64 /* "Message Proper" size */ 9911194Ssam #define MAXRETRY 4 10011194Ssam 10111194Ssam /* 10211208Ssam * Device registers 10311194Ssam */ 10411194Ssam struct hydevice { 10511208Ssam short hyd_wcr; /* word count (negated) */ 10611208Ssam u_short hyd_bar; /* bus address bits 15-0 */ 10711208Ssam u_short hyd_csr; /* control and status */ 10811208Ssam u_short hyd_dbuf; /* data buffer */ 10911194Ssam }; 11011194Ssam 11111194Ssam /* 11211208Ssam * CSR bit layout 11311194Ssam */ 11411194Ssam #define S_ERROR 0100000 /* error */ 11511194Ssam #define S_NEX 0040000 /* non-existent memory error */ 11611194Ssam #define S_ATTN 0020000 /* attn (always zero) */ 11711194Ssam #ifdef PI13 11811194Ssam #define S_STKINTR 0010000 /* stacked interrupt */ 11911194Ssam #else 12011194Ssam #define S_MAINT 0010000 /* maintenance (not used) */ 12111194Ssam #endif 12211194Ssam #define S_A 0004000 /* device status A (recieve data available) */ 12311194Ssam #define S_B 0002000 /* device status B (normal termination) */ 12411194Ssam #define S_C 0001000 /* device status C (abnormal termination) */ 12511194Ssam #ifdef PI13 12611194Ssam #define S_POWEROFF 0000400 /* power off indicator */ 12711194Ssam #else 12811194Ssam #define S_CYCLE 0000400 /* cycle (not used) */ 12911194Ssam #endif 13011194Ssam #define S_READY 0000200 /* ready */ 13111194Ssam #define S_IE 0000100 /* interrupt enable */ 13211194Ssam #define S_XBA 0000060 /* bus address bit bits 17 and 16 */ 13311194Ssam #define S_CLRINT 0000014 /* clear stacked interrupt */ 13411194Ssam #define S_IATTN 0000010 /* interrupt on attention only */ 13511194Ssam #define S_WC 0000004 /* interrupt on word count == 0 only */ 13611194Ssam #define S_IATTNWC 0000000 /* interrupt on word count == 0 and attention */ 13711194Ssam #define S_BURST 0000002 /* burst mode DMA (not used) */ 13811194Ssam #define S_GO 0000001 /* go */ 13911194Ssam 14011208Ssam #define XBASHIFT 12 14111194Ssam 142*24462Skarels #define HY_CSR_BITS "\20\ 143*24462Skarels \20ERROR\17NEX\16ATTN\15STKINTR\14RECV_DATA\13NORMAL\12ABNORMAL\11POWER\ 144*24462Skarels \10READY\07IENABLE\06XBA17\05XBA16\04IATTN\03IWC\02BURST\01GO" 14511194Ssam 14611194Ssam /* 14711194Ssam * PI13 status conditions 14811194Ssam */ 14911208Ssam #define HYS_RECVDATA(x) (((x)->hyd_csr & S_A) != 0) /* get adapter data */ 15011208Ssam #define HYS_NORMAL(x) (((x)->hyd_csr & S_B) != 0) /* done normally */ 15111208Ssam #define HYS_ABNORMAL(x) (((x)->hyd_csr & S_C) != 0) /* done abnormally */ 15211208Ssam #define HYS_ERROR(x) (((x)->hyd_csr & S_ERROR) != 0) /* error condition */ 15311208Ssam #define HYS_DONE(x) (((x)->hyd_csr & (S_ERROR|S_B|S_C)) != 0) 15411194Ssam 15511194Ssam /* 15611194Ssam * Function Codes for the Hyperchannel Adapter 15711194Ssam * The codes are offset so they can be "or"ed into 15811194Ssam * the reg data buffer 15911194Ssam */ 16011194Ssam #define HYF_XMITMSG 0x04 /* transmit message */ 16111194Ssam #define HYF_XMITDATA 0x08 /* transmit associated data */ 16211194Ssam #define HYF_XMITLSTDATA 0x0C /* transmit last associated data */ 16311194Ssam #define HYF_XMITLOCMSG 0x10 /* transmit local message */ 16411194Ssam #define HYF_INPUTMSG 0x24 /* input message proper */ 16511194Ssam #define HYF_INPUTDATA 0x28 /* input assiciated data */ 16611194Ssam #define HYF_STATUS 0x40 /* request status */ 16711194Ssam #define HYF_DUMPREGS 0x50 /* dump extention registers */ 16811194Ssam #define HYF_MARKP0 0x60 /* mark down port 0 */ 16911194Ssam #define HYF_MARKP1 0x64 /* mark down port 1 */ 17011194Ssam #define HYF_MARKP2 0x68 /* mark down port 2 */ 17111194Ssam #define HYF_MARKP3 0x6C /* mark down port 3 */ 17211194Ssam #define HYF_MP0RR 0x70 /* mark down port 0 and reroute messages */ 17311194Ssam #define HYF_MP1RR 0x74 /* mark down port 1 and reroute messages */ 17411194Ssam #define HYF_MP2RR 0x78 /* mark down port 2 and reroute messages */ 17511194Ssam #define HYF_MP3RR 0x7C /* mark down port 3 and reroute messages */ 17611194Ssam #define HYF_RSTATS 0xA0 /* read statistics */ 17711194Ssam #define HYF_RCSTATS 0xA4 /* read and clear statistics */ 17811194Ssam #define HYF_SETTEST 0xC0 /* enable test operations *set test mode) */ 17911194Ssam #define HYF_SADDR_LEN 0xC4 /* test mode: set address and length */ 18011194Ssam #define HYF_WBUFF 0xC8 /* test mode: write buffer */ 18111194Ssam #define HYF_RBUFF 0xCC /* test mode: read buffer */ 18211194Ssam #define HYF_CLRADAPTER 0xE0 /* clear adapter */ 18311194Ssam #define HYF_END_OP 0xE4 /* end operation */ 18411194Ssam #define HYF_CLRWFMSG 0xE6 /* clear wait for mwssage */ 18511194Ssam #define HYF_WAITFORMSG 0xE8 /* wait for message */ 186