123297Smckusick /* 235322Sbostic * Copyright (c) 1988 Regents of the University of California. 335322Sbostic * All rights reserved. 423297Smckusick * 535322Sbostic * This code is derived from software contributed to Berkeley by 635322Sbostic * Tektronix Inc. 724462Skarels * 8*44560Sbostic * %sccs.include.redist.c% 935322Sbostic * 10*44560Sbostic * @(#)if_hyreg.h 7.3 (Berkeley) 06/28/90 1135322Sbostic */ 1235322Sbostic 1335322Sbostic /* 1424462Skarels * Modifications from Berkeley 4.2 BSD 1524462Skarels * Copyright (c) 1983, Tektronix Inc. 1624462Skarels * All Rights Reserved 1723297Smckusick */ 1811194Ssam 1911194Ssam /* 2011194Ssam * Network Systems Corporation Hyperchannel interface 2111194Ssam * 2211194Ssam * supports A410 adapter interfaced via a DEC DR-11B, NSC PI-13 or PI-14 2311194Ssam * (PI-14 is a PI-13 with different line drivers, software is 2411194Ssam * identical to a PI-13) 2511194Ssam * 2611194Ssam * Written by Steve Glaser, Tektronix Inc., July 1982 2711194Ssam * 2811194Ssam * NOTE: 2911194Ssam * 3011194Ssam * DR11B code has not been fully checked out with 4.1a. 3111194Ssam * The first adapters at Tek came with DR11Bs, and the code once worked, 3211194Ssam * but those have been upgraded to PI-13s. 3311194Ssam */ 3411194Ssam 3511194Ssam /* 3611194Ssam * The HYPERchannel driver sends and receives messages formatted: 3711194Ssam * 3811194Ssam * +---------------------------------------+ --- 3911194Ssam * | | /|\ 4011194Ssam * | HYPERchannel adapter header (hy_hdr) | | 4111194Ssam * | | | 4211194Ssam * +---------------------------------------+ | 4311194Ssam * | | | 4411194Ssam * | Internet Protocol header (ip) | message proper 4511194Ssam * | | (64 bytes max) 4611194Ssam * +---------------------------------------+ | 4711194Ssam * | | | 4811194Ssam * | TCP header + user data | | 4911194Ssam * | (if it all fits here) | | 5011194Ssam * | | \|/ 5111194Ssam * +---------------------------------------+ --- 5211194Ssam * 5311194Ssam * +---------------------------------------+ --- 5411194Ssam * | | /|\ 5511194Ssam * | | | 5611194Ssam * | TCP header + user data | associated data 5711194Ssam * | | | 5811194Ssam * | | \|/ 5911194Ssam * +---------------------------------------+ --- 6011194Ssam * 6111194Ssam * If all of the datagram will fit in the message proper (including 6211194Ssam * the TCP header and user data) the entire datagram is passed in 6311194Ssam * the message proper and the associated data feature of the HYPERchannel 6411194Ssam * is not used. 6511194Ssam * 6611194Ssam * The mapping from internet addresses to HYPERchannel addresses is: 6711194Ssam * 6811194Ssam * 0 7 8 15 16 31 6911194Ssam * +---------+---------+-----------------------+ 7011194Ssam * | network | special | HYPERchannel address | 7111194Ssam * +---------+---------+-----------------------+ 7211194Ssam * 7311194Ssam * |<------------ internet address ----------->| 7411194Ssam * 7511194Ssam * The hyperchannel address is decoded as follows: 7611194Ssam * 7711194Ssam * 0 7 8 13 14 15 7811194Ssam * +-------------------+----------------+------+ 7911194Ssam * | adapter number | zero | port | 8011194Ssam * +-------------------+----------------+------+ 8111194Ssam * 8211194Ssam * The low 2 bits are port number (interpreted by hyperchannel hardware). 8311194Ssam * 8411194Ssam * The encoding of special bits is: 8511194Ssam * 8611194Ssam * 00 normal packet 8711194Ssam * 8811194Ssam * 01 loop this packet back to the sender at the 8911194Ssam * specified adapter (ip header source/destination addresses 9011194Ssam * swapped before sending, command bits added to tell the 9111194Ssam * remote HYPERchannel adapter debug & performance studies] 9211194Ssam * this code acts like 02 (below) if the ip destination (before 9311194Ssam * any swapping) and the destination address don't match (e.g. 9411194Ssam * this packet is being routed through a gateway) 9511194Ssam * 9611194Ssam * 02 loop this packet back to the sender at the 9711194Ssam * specified adapter, but go through the specified adapter's 9811194Ssam * IP. This is for testing IP's store and forward mechanism. 9911194Ssam * 10011194Ssam * other undefined, currently treated as normal packet 10111194Ssam * 10211194Ssam */ 10311194Ssam #define MPSIZE 64 /* "Message Proper" size */ 10411194Ssam #define MAXRETRY 4 10511194Ssam 10611194Ssam /* 10711208Ssam * Device registers 10811194Ssam */ 10911194Ssam struct hydevice { 11011208Ssam short hyd_wcr; /* word count (negated) */ 11111208Ssam u_short hyd_bar; /* bus address bits 15-0 */ 11211208Ssam u_short hyd_csr; /* control and status */ 11311208Ssam u_short hyd_dbuf; /* data buffer */ 11411194Ssam }; 11511194Ssam 11611194Ssam /* 11711208Ssam * CSR bit layout 11811194Ssam */ 11911194Ssam #define S_ERROR 0100000 /* error */ 12011194Ssam #define S_NEX 0040000 /* non-existent memory error */ 12111194Ssam #define S_ATTN 0020000 /* attn (always zero) */ 12211194Ssam #ifdef PI13 12311194Ssam #define S_STKINTR 0010000 /* stacked interrupt */ 12411194Ssam #else 12511194Ssam #define S_MAINT 0010000 /* maintenance (not used) */ 12611194Ssam #endif 12711194Ssam #define S_A 0004000 /* device status A (recieve data available) */ 12811194Ssam #define S_B 0002000 /* device status B (normal termination) */ 12911194Ssam #define S_C 0001000 /* device status C (abnormal termination) */ 13011194Ssam #ifdef PI13 13111194Ssam #define S_POWEROFF 0000400 /* power off indicator */ 13211194Ssam #else 13311194Ssam #define S_CYCLE 0000400 /* cycle (not used) */ 13411194Ssam #endif 13511194Ssam #define S_READY 0000200 /* ready */ 13611194Ssam #define S_IE 0000100 /* interrupt enable */ 13711194Ssam #define S_XBA 0000060 /* bus address bit bits 17 and 16 */ 13811194Ssam #define S_CLRINT 0000014 /* clear stacked interrupt */ 13911194Ssam #define S_IATTN 0000010 /* interrupt on attention only */ 14011194Ssam #define S_WC 0000004 /* interrupt on word count == 0 only */ 14111194Ssam #define S_IATTNWC 0000000 /* interrupt on word count == 0 and attention */ 14211194Ssam #define S_BURST 0000002 /* burst mode DMA (not used) */ 14311194Ssam #define S_GO 0000001 /* go */ 14411194Ssam 14511208Ssam #define XBASHIFT 12 14611194Ssam 14724462Skarels #define HY_CSR_BITS "\20\ 14824462Skarels \20ERROR\17NEX\16ATTN\15STKINTR\14RECV_DATA\13NORMAL\12ABNORMAL\11POWER\ 14924462Skarels \10READY\07IENABLE\06XBA17\05XBA16\04IATTN\03IWC\02BURST\01GO" 15011194Ssam 15111194Ssam /* 15211194Ssam * PI13 status conditions 15311194Ssam */ 15411208Ssam #define HYS_RECVDATA(x) (((x)->hyd_csr & S_A) != 0) /* get adapter data */ 15511208Ssam #define HYS_NORMAL(x) (((x)->hyd_csr & S_B) != 0) /* done normally */ 15611208Ssam #define HYS_ABNORMAL(x) (((x)->hyd_csr & S_C) != 0) /* done abnormally */ 15711208Ssam #define HYS_ERROR(x) (((x)->hyd_csr & S_ERROR) != 0) /* error condition */ 15811208Ssam #define HYS_DONE(x) (((x)->hyd_csr & (S_ERROR|S_B|S_C)) != 0) 15911194Ssam 16011194Ssam /* 16111194Ssam * Function Codes for the Hyperchannel Adapter 16211194Ssam * The codes are offset so they can be "or"ed into 16311194Ssam * the reg data buffer 16411194Ssam */ 16511194Ssam #define HYF_XMITMSG 0x04 /* transmit message */ 16611194Ssam #define HYF_XMITDATA 0x08 /* transmit associated data */ 16711194Ssam #define HYF_XMITLSTDATA 0x0C /* transmit last associated data */ 16811194Ssam #define HYF_XMITLOCMSG 0x10 /* transmit local message */ 16911194Ssam #define HYF_INPUTMSG 0x24 /* input message proper */ 17011194Ssam #define HYF_INPUTDATA 0x28 /* input assiciated data */ 17111194Ssam #define HYF_STATUS 0x40 /* request status */ 17211194Ssam #define HYF_DUMPREGS 0x50 /* dump extention registers */ 17311194Ssam #define HYF_MARKP0 0x60 /* mark down port 0 */ 17411194Ssam #define HYF_MARKP1 0x64 /* mark down port 1 */ 17511194Ssam #define HYF_MARKP2 0x68 /* mark down port 2 */ 17611194Ssam #define HYF_MARKP3 0x6C /* mark down port 3 */ 17711194Ssam #define HYF_MP0RR 0x70 /* mark down port 0 and reroute messages */ 17811194Ssam #define HYF_MP1RR 0x74 /* mark down port 1 and reroute messages */ 17911194Ssam #define HYF_MP2RR 0x78 /* mark down port 2 and reroute messages */ 18011194Ssam #define HYF_MP3RR 0x7C /* mark down port 3 and reroute messages */ 18111194Ssam #define HYF_RSTATS 0xA0 /* read statistics */ 18211194Ssam #define HYF_RCSTATS 0xA4 /* read and clear statistics */ 18311194Ssam #define HYF_SETTEST 0xC0 /* enable test operations *set test mode) */ 18411194Ssam #define HYF_SADDR_LEN 0xC4 /* test mode: set address and length */ 18511194Ssam #define HYF_WBUFF 0xC8 /* test mode: write buffer */ 18611194Ssam #define HYF_RBUFF 0xCC /* test mode: read buffer */ 18711194Ssam #define HYF_CLRADAPTER 0xE0 /* clear adapter */ 18811194Ssam #define HYF_END_OP 0xE4 /* end operation */ 18911194Ssam #define HYF_CLRWFMSG 0xE6 /* clear wait for mwssage */ 19011194Ssam #define HYF_WAITFORMSG 0xE8 /* wait for message */ 191