135321Sbostic /* 235321Sbostic * Copyright (c) 1988 Regents of the University of California. 335321Sbostic * All rights reserved. 435321Sbostic * 535321Sbostic * This code is derived from software contributed to Berkeley by 635321Sbostic * Advanced Computer Communications. 735321Sbostic * 8*44559Sbostic * %sccs.include.redist.c% 935321Sbostic * 10*44559Sbostic * @(#)if_hdhreg.h 7.3 (Berkeley) 06/28/90 1135321Sbostic */ 1224434Skarels 1324434Skarels /* 1424434Skarels * ACC IF-11/HDH interface 1524434Skarels */ 1624434Skarels 1724434Skarels struct hdhregs { /* device registers */ 1824434Skarels u_short csr; /* control and status register */ 1924434Skarels u_char iochn; /* logical channel */ 2024434Skarels u_char ioadx; /* address extension (A16,A17) */ 2124434Skarels u_short ioadl; /* buffer address (A0-A15) */ 2224434Skarels u_short iocnt; /* byte count */ 2324434Skarels u_char iofcn; /* UMC funciton code */ 2424434Skarels u_char iosbf; /* UMC subfunction code */ 2524434Skarels u_char ioini; /* comm regs valid flag */ 2624434Skarels u_char staack; /* interrupt acknowledge flag */ 2724434Skarels u_char ionmi; /* NMI routine active flag */ 2824434Skarels u_char ioxfrg; /* UMR transfer grant flag */ 2924434Skarels u_char stachn; /* interrupt channel number */ 3024434Skarels u_char statyp; /* interrupt type code */ 3124434Skarels u_char stacc; /* completion function code */ 3224434Skarels u_char stacs; /* completion subfunction code */ 3324434Skarels u_short stacnt; /* completion byte count */ 3424434Skarels }; 3524434Skarels 3624434Skarels /* defines for CSR */ 3724434Skarels 3824434Skarels #define HDH_UER 0100000 /* UMC error condition */ 3924434Skarels #define HDH_NXM 0040000 /* non-existent memory error */ 4024434Skarels #define HDH_PER 0020000 /* UNIBUS parity error */ 4124434Skarels #define HDH_ZRUN 0010000 /* Z80 running */ 4224434Skarels #define HDH_ZGO 0004000 /* Z80 not in wait state */ 4324434Skarels #define HDH_MBLK 0000200 /* memory swap state (0=main, 1=srv) */ 4424434Skarels #define HDH_SRV 0000100 /* select UMC service memory */ 4524434Skarels #define HDH_MAIN 0000040 /* select UMC main memory */ 4624434Skarels #define HDH_DMA 0000020 /* DMA enable */ 4724434Skarels #define HDH_WRT 0000010 /* DMA write enable */ 4824434Skarels #define HDH_IEN 0000004 /* interrupt enable */ 4924434Skarels #define HDH_RST 0000002 /* reset */ 5024434Skarels #define HDH_NMI 0000001 /* cause NMI */ 5124434Skarels 5224434Skarels #define HDH_BITS \ 5324434Skarels "\10\20UER\17NXM\16PER\15ZRUN\14ZGO\10MBLK\7SRV\6MAIN\5DMA\4WRT\3IEN\2RST\1NMI" 5424434Skarels 5524434Skarels /* start i/o function code definitions */ 5624434Skarels 5724434Skarels #define HDHWRT 0 /* write to if-11 */ 5824434Skarels #define HDHRDB 1 /* read from if-11 */ 5924434Skarels #define HDHSTR 2 /* stream flag */ 6024434Skarels #define HDHEOS 6 /* end of stream flag */ 6124434Skarels #define HDHABT 8 /* abort flag */ 6224434Skarels #define HDHUMR 16 /* UMR protocol flag */ 6324434Skarels 6424434Skarels /* interrupt type definitions */ 6524434Skarels 6624434Skarels #define HDHSACK 0 /* start i/o ack */ 6724434Skarels #define HDHDONE 1 /* i/o completion */ 6824434Skarels #define HDHXREQ 2 /* UMR protocol transfer request */ 6924434Skarels 7024434Skarels /* i/o completion codes */ 7124434Skarels 7224434Skarels #define HDHIOCOK 0001 /* successful completion */ 7324434Skarels #define HDHIOCOKP 0002 /* successful completion, more data pending */ 7424434Skarels #define HDHIOCABT 0361 /* i/o aborted */ 7524434Skarels #define HDHIOCERR 0321 /* program error */ 7624434Skarels #define HDHIOCOVR 0363 /* overrun error */ 7724434Skarels #define HDHIOCUBE 0374 /* non-existant memory or unibus error */ 7824434Skarels 7924434Skarels /* UMR protocol transfer grant code definitions */ 8024434Skarels 8124434Skarels #define HDHXEVN 1 /* start with even address */ 8224434Skarels #define HDHXODD 2 /* start with odd address */ 8324434Skarels #define HDHNUMR 4 /* non-UMR transfer */ 8424434Skarels #define HDHXABT 8 /* abort transfer */ 8524434Skarels 8624434Skarels /* HDH supervisor request code definitions */ 8724434Skarels #define HDHINIT 0x42 /* SYSINIT opcode */ 8824434Skarels 8924434Skarels #define HDHSUP 0xf0 /* supervisor HDH status/line control prefix */ 9024434Skarels #define HDHIMP 0x400 /* IMP line up modifier */ 9124434Skarels #define HDHREFL 0x800 /* reflect mode modifier */ 9224434Skarels #define HDHINLB 0x1000 /* internal loopback modifier */ 9324434Skarels #define HDHEXLP 0x2000 /* external loopback modifier */ 9426284Skarels #define HDHRQST (HDHSUP+0x0000) /* line status request */ 9526284Skarels #define HDHRQUP (HDHSUP+0x0100) /* line up request */ 9626284Skarels #define HDHRQDN (HDHSUP+0x0200) /* line down request */ 9724434Skarels 9824434Skarels /* HDH supervisor reply code definitions */ 9924434Skarels 10026284Skarels #define HDHIACK (HDHSUP+0x4200) /* line init ack */ 10126284Skarels #define HDHLNUP (HDHSUP+0x0100) /* line up reply */ 10226284Skarels #define HDHLNDN (HDHSUP+0x0200) /* line down reply */ 10326284Skarels #define HDHLNACK (HDHSUP+0x0300) /* ack line up request (but line is down now) */ 10426284Skarels #define HDHTIMO (HDHSUP+0x0400) /* line timeout */ 10526284Skarels #define HDHLOOP (HDHSUP+0x0500) /* loopback message */ 10626284Skarels #define HDHDTERR (HDHSUP+0x0600) /* host data error detected */ 10726284Skarels #define HDHSQRCV (HDHSUP+0x0700) /* HDLC sequence error detected by IMP */ 10826284Skarels #define HDHSQERR (HDHSUP+0x0800) /* HDLC sequence error detected by if-11 */ 109