1 /* 2 * Copyright (c) 1982 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)if_exreg.h 6.2 (Berkeley) 06/08/85 7 */ 8 9 10 struct exdevice { 11 char xd_porta; /* write on porta resets EXOS */ 12 char xd_pad_a; 13 char xd_portb; /* write on portb interrupts EXOS */ 14 /* read on portb returns status bits */ 15 char xd_pad_b; 16 }; 17 18 /* EXOS I/O PORT A write definitions */ 19 #define EX_RESET 0 /* value doesn't really matter... */ 20 21 /* EXOS I/O PORT B write definitions */ 22 #define EX_NTRUPT 0 23 24 /* EXOS I/O PORT B read definitions */ 25 #define EX_TESTOK 1 /* set when self-diagnostics passed */ 26 #define EX_UNREADY (1<<3) /* set until EXOS ready to read from B */ 27 28 /* message buffer status field definitions */ 29 #define MH_OWNER 1 /* mask for status bit for owner */ 30 #define MH_HOST 0 /* if 0, the host owns the buffer */ 31 #define MH_EXOS 1 /* if 1, the EXOS owns the buffer */ 32 33 /* EXOS Link Level request codes */ 34 #define LLTRANSMIT 0xC /* send a packet */ 35 #define LLRTRANSMIT 0xE /* send a packet, and self-receive */ 36 #define LLRECEIVE 0xD /* receive a packet */ 37 #define LLNET_MODE 0x8 /* read/write mode control objects */ 38 #define LLNET_ADDRS 0x9 /* read/write receive address slots */ 39 #define LLNET_RECV 0xA /* read/alter receive slot enable bit */ 40 #define LLNET_STSTCS 0xB /* read/reset network statistics objects */ 41 42 /* Link Level return codes common to all requests */ 43 #define LL_OK 0 /* successful completion */ 44 #define LLX_MODE 0xA1 /* EXOS not in link level mode (impossible) */ 45 46 /* LLTRANSMIT unique return codes */ 47 #define LLXM_1RTRY 0x1 /* successful xmission, 1 retry */ 48 #define LLXM_RTRYS 0x2 /* successful xmission, more than 1 retry */ 49 #define LLXM_NSQE 0x8 /* successful xmission, no SQE TEST signal */ 50 #define LLXM_CLSN 0x10 /* xmission failed, excess retries */ 51 #define LLXM_NCS 0x20 /* xmission failed, no carrier sense */ 52 #define LLXM_LNGTH 0x40 /* xmission failed, bad packet length */ 53 #define XMIT_BITS "\7\7LENGTH\6CARRIER\5XCLSNS\4SQETST" 54 #define LLXM_ERROR (LLXM_NSQE|LLXM_CLSN|LLXM_NCS|LLXM_LNGTH) 55 56 /* LLRECEIVE unique return codes */ 57 #define LLRC_TRUNC 0x4 /* pkt received, but truncated to fit buffer */ 58 #define LLRC_ALIGN 0x10 /* pkt received, but with alignment error */ 59 #define LLRC_CRC 0x20 /* pkt received, but with CRC error */ 60 #define LLRC_BUFLEN 0x40 /* no pkt received, buffer less than 64 bytes */ 61 /* this should never happen here */ 62 #define RECV_BITS "\7\7BUFLEN\6CRC\5ALIGN\3TRUNC" 63 64 /* LLNET_ADDRS unique return codes */ 65 #define LLNA_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */ 66 #define LLNA_BADADDR 0xD3 /* invalid address for designated slot */ 67 68 /* LLNET_RECV unique return codes */ 69 #define LLNR_BADSLOT 0xD1 /* slot doesn't exist or can't be accessed */ 70 #define LLNR_BADADDR 0xD2 /* designated slot was empty */ 71 72 /* address slot object indices */ 73 #define NULLSLOT 0 /* the null slot */ 74 #define MINMCSLOT 1 /* minimum multicast slot index */ 75 #define MAXMCSLOT 8 /* default maximum multicast slot index */ 76 #define PHYSSLOT 253 /* physical slot index */ 77 #define UNVRSSLOT 254 /* universal slot index */ 78 #define BROADSLOT 255 /* broadcast slot index */ 79 80 /* request mask bit definitions */ 81 #define WRITE_OBJ 1 /* write the object */ 82 #define READ_OBJ 2 /* read the object */ 83 #define ENABLE_RCV 4 /* enable reception on designated slot */ 84 85 /* NET_MODE options mask bit definitions */ 86 #define OPT_ALIGN 0x10 /* receive packets with alignment errors */ 87 #define OPT_CRC 0x20 /* receive packets with CRC errors */ 88 #define OPT_DSABLE 0x80 /* disconnect controller hardware */ 89 90 /* NET_MODE mode field value definitions */ 91 #define MODE_OFF 0 /* stop transmission and reception */ 92 #define MODE_PERF 1 /* perfect multicast address filtering */ 93 #define MODE_HW 2 /* hardware-only multicast address filtering */ 94 #define MODE_PROM 3 /* promiscuous reception */ 95 96 #define NFRAGMENTS 1 /* number fragments that the EXOS will scatter/gather */ 97 #define EXMAXRBUF 1520 /* per EXOS 101 manual 5.3.7 (maybe 1518 would do) */ 98 99 /* 100 * N.B. Structures below are carefully constructed so that 101 * they correspond to the message formats that NX firmware 102 * defines. None of them should contain any compiler-instigated 103 * padding. Be especially careful about VAX C longword alignment! 104 */ 105 106 struct stat_array { 107 u_long sa_fsent; /* frames sent without errors */ 108 u_long sa_xsclsn; /* frames aborted excess collisions */ 109 u_long sa_nsqe; /* frames subject to heartbeat failure */ 110 u_long sa_undef; /* undefined (TDR on EXOS 101) */ 111 u_long sa_frcvd; /* frames received no errors */ 112 u_long sa_align; /* frames received alignment error */ 113 u_long sa_crc; /* frames received crc error */ 114 u_long sa_flost; /* frames lost */ 115 }; 116 117 struct buf_blk { /* packet/buffer block descriptor */ 118 u_short bb_len; /* length of block, in bytes */ 119 u_short bb_addr[2]; /* address of block */ 120 /* 121 * Array above is really a single u_long field. 122 * We kludge its definition to defeat word-alignment. 123 * Access would look like: 124 * longaddr = *(u_long *)bp->.mb_er.er_blks[0].bb_addr; 125 */ 126 }; 127 128 struct net_mode { /* read/write mode control objects */ 129 /*12*/ u_char nm_rqst; /* request code */ 130 /*13*/ u_char nm_rply; /* reply code */ 131 /*14*/ u_char nm_mask; /* bit-wise switches for read, write */ 132 /*15*/ u_char nm_optn; /* acceptable packet reception errors */ 133 /*16*/ u_char nm_mode; /* EXOS filtering mode */ 134 /*17*/ 135 }; 136 137 struct net_addrs { /* read/write receive address slots */ 138 /*12*/ u_char na_rqst; /* request code */ 139 /*13*/ u_char na_rply; /* reply code */ 140 /*14*/ u_char na_mask; /* bit-wise switches for read, write */ 141 /*15*/ u_char na_slot; /* index of address slot */ 142 /*16*/ u_char na_addrs[6]; /* address read and/or written */ 143 /*22*/ 144 }; 145 146 struct net_recv { /* read/alter receive slot enable bit */ 147 /*12*/ u_char nr_rqst; /* request code */ 148 /*13*/ u_char nr_rply; /* reply code */ 149 /*14*/ u_char nr_mask; /* bit-wise switches for read, write */ 150 /*15*/ u_char nr_slot; /* index of address slot */ 151 /*16*/ 152 }; 153 154 struct net_ststcs { /* read/reset network statistics objects */ 155 /*12*/ u_char ns_rqst; /* request code */ 156 /*13*/ u_char ns_rply; /* reply code */ 157 /*14*/ u_char ns_mask; /* bit-wise switches for read, write */ 158 /*15*/ u_char ns_rsrv; /* reserved for EXOS */ 159 /*16*/ u_short ns_nobj; /* number of objects to work on */ 160 /*18*/ u_short ns_xobj; /* index of first object to work on */ 161 /*20*/ u_long ns_bufp; /* pointer to statistics buffer */ 162 /*24*/ 163 }; 164 165 struct enet_xmit { /* send a packet on the Ethernet */ 166 /*12*/ u_char et_rqst; /* request code */ 167 /*13*/ u_char et_rply; /* reply code */ 168 /*14*/ u_char et_slot; /* address slot matching dest address */ 169 /*15*/ u_char et_nblock; /* number of blocks composing packet */ 170 /*16*/ struct buf_blk et_blks[NFRAGMENTS]; /* array of block descriptors */ 171 /*22-64*/ 172 }; 173 174 struct enet_recv { /* receive a packet on the Ethernet */ 175 /*12*/ u_char er_rqst; /* request code */ 176 /*13*/ u_char er_rply; /* reply code */ 177 /*14*/ u_char er_slot; /* address slot matching dest address */ 178 /*15*/ u_char er_nblock; /* number of blocks composing buffer */ 179 /*16*/ struct buf_blk er_blks[NFRAGMENTS]; /* array of block descriptors */ 180 /*22-64*/ 181 }; 182 183 /* we send requests and receive replys with the EXOS using this structure */ 184 struct ex_msg { 185 /*00*/ u_short mb_link; /* address of next message buffer */ 186 /*02*/ u_char mb_rsrv; /* reserved for use by EXOS */ 187 /*03*/ u_char mb_status; /* used bit-wise for message protocol */ 188 /*04*/ u_short mb_length; /* length, in bytes, of the rest */ 189 /*06*/ short mb_1rsrv; /* reserved for used by EXOS */ 190 /*08*/ long mb_mid; /* available to user */ 191 /*12*/ union mb_all { 192 struct net_mode mb_net_mode; 193 struct net_addrs mb_net_addrs; 194 struct net_recv mb_net_recv; 195 struct net_ststcs mb_net_ststcs; 196 struct enet_xmit mb_enet_xmit; 197 struct enet_recv mb_enet_recv; 198 } mb_all; 199 /* following field is used only by host, not read by board */ 200 struct ex_msg *mb_next; /* host's pointer to next message */ 201 }; 202 #define mb_nm mb_all.mb_net_mode 203 #define mb_na mb_all.mb_net_addrs 204 #define mb_nr mb_all.mb_net_recv 205 #define mb_ns mb_all.mb_net_ststcs 206 #define mb_et mb_all.mb_enet_xmit 207 #define mb_er mb_all.mb_enet_recv 208 #define mb_rqst mb_nm.nm_rqst 209 #define mb_rply mb_nm.nm_rply 210 #define MBDATALEN (sizeof(union mb_all)+6) 211 212 struct confmsg { 213 /*00*/ u_short cm_1rsrv; /* reserved, must be 1 */ 214 /*02*/ char cm_vc[4]; /* returns ASCII version code */ 215 /*06*/ u_char cm_cc; /* returns config completion code */ 216 /*07*/ u_char cm_opmode; /* specifies operation mode */ 217 /*08*/ u_short cm_dfo; /* specifies host data format option */ 218 /*10*/ u_char cm_dcn1; /* reserved, must be 1 */ 219 /*11*/ u_char cm_2rsrv[2]; /* reserved, must be 0 */ 220 /*13*/ u_char cm_ham; /* specifies host address mode */ 221 /*14*/ u_char cm_3rsrv; /* reserved, must be 0 */ 222 /*15*/ u_char cm_mapsiz; /* reserved, must be 0 */ 223 /*16*/ u_char cm_byteptrn[4]; /* host data format option test pattern */ 224 /*20*/ u_short cm_wordptrn[2]; 225 /*24*/ u_long cm_lwordptrn; 226 /*28*/ u_char cm_rsrvd[20]; 227 /*48*/ u_long cm_mba; /* use 0xFFFFFFFF in link level mode */ 228 /*52*/ u_char cm_nproc; /* use 0xFF in link level mode */ 229 /*53*/ u_char cm_nmbox; /* use 0xFF in link level mode */ 230 /*54*/ u_char cm_nmcast; /* use 0xFF in link level mode */ 231 /*55*/ u_char cm_nhost; /* use 1 in link level mode */ 232 233 /* the next five parameters define the request message queue */ 234 /*56*/ u_long cm_h2xba; /* base address of message queue */ 235 /*60*/ u_short cm_h2xhdr; /* address offset of msg Q header */ 236 /*62*/ u_char cm_h2xtyp; /* interrupt type */ 237 /*63*/ u_char cm_h2xval; /* interrupt value (not used) */ 238 /*64*/ u_short cm_h2xaddr; /* interrupt vector */ 239 /*66*/ u_short cm_h2xpad; /* pad out unused portion of vector */ 240 241 /* the next five parameters define the reply message queue */ 242 /*68*/ u_long cm_x2hba; /* base address of message queue */ 243 /*72*/ u_short cm_x2hhdr; /* address offset of msg Q header */ 244 /*74*/ u_char cm_x2htyp; /* interrupt type */ 245 /*75*/ u_char cm_x2hval; /* interrupt value (not used) */ 246 /*76*/ u_short cm_x2haddr; /* interrupt vector */ 247 /*78*/ u_short cm_x2hpad; /* pad out unused portion of vector */ 248 /*80*/ 249 }; 250 251