1*4772Swnj /* if_enreg.h 4.2 81/11/07 */ 24765Swnj 34765Swnj /* 44765Swnj * Xerox experimental ethernet registers. 54765Swnj * 64765Swnj * N.B.: status register and device address are read/write, 74765Swnj * device address is read-only, rest are WRITE ONLY! 84765Swnj */ 94765Swnj struct endevice { 104765Swnj short en_owc; /* output word count (10 bits) */ 114765Swnj short en_oba; /* output buffer address */ 124765Swnj short en_ostat; /* output control and status */ 134765Swnj short en_odelay; /* output start delay, 25usec units */ 144765Swnj short en_iwc; /* input word count */ 154765Swnj short en_iba; /* input buffer address */ 164765Swnj short en_istat; /* input csr */ 174765Swnj short en_addr; /* ~device address (low 8 bits) */ 184765Swnj }; 194765Swnj 204765Swnj /* 214765Swnj * Control and status bits. 224765Swnj */ 234765Swnj #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ 244765Swnj #define EN_OERROR 0x8000 /* collision or output underrun */ 254765Swnj #define EN_OPDONE 0x0080 /* previous operation completed */ 264765Swnj #define EN_IEN 0x0040 /* enable interrupt when DONE */ 27*4772Swnj #define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */ 284765Swnj #define EN_GO 0x0001 /* start op bit */ 294765Swnj 304765Swnj #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" 314765Swnj 324765Swnj #define spl_enet() spl5() 33