1*4765Swnj /* if_enreg.h 4.1 81/11/07 */ 2*4765Swnj 3*4765Swnj /* 4*4765Swnj * Xerox experimental ethernet registers. 5*4765Swnj * 6*4765Swnj * N.B.: status register and device address are read/write, 7*4765Swnj * device address is read-only, rest are WRITE ONLY! 8*4765Swnj */ 9*4765Swnj struct endevice { 10*4765Swnj short en_owc; /* output word count (10 bits) */ 11*4765Swnj short en_oba; /* output buffer address */ 12*4765Swnj short en_ostat; /* output control and status */ 13*4765Swnj short en_odelay; /* output start delay, 25usec units */ 14*4765Swnj short en_iwc; /* input word count */ 15*4765Swnj short en_iba; /* input buffer address */ 16*4765Swnj short en_istat; /* input csr */ 17*4765Swnj short en_addr; /* ~device address (low 8 bits) */ 18*4765Swnj }; 19*4765Swnj 20*4765Swnj /* 21*4765Swnj * Control and status bits. 22*4765Swnj */ 23*4765Swnj #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ 24*4765Swnj #define EN_OERROR 0x8000 /* collision or output underrun */ 25*4765Swnj #define EN_OPDONE 0x0080 /* previous operation completed */ 26*4765Swnj #define EN_IEN 0x0040 /* enable interrupt when DONE */ 27*4765Swnj #define EN_PROMISCUOOS 0x0002 /* promiscuous, input any packet */ 28*4765Swnj #define EN_GO 0x0001 /* start op bit */ 29*4765Swnj 30*4765Swnj #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" 31*4765Swnj 32*4765Swnj #define spl_enet() spl5() 33