123291Smckusick /* 229279Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 3*35319Sbostic * All rights reserved. 423291Smckusick * 5*35319Sbostic * Redistribution and use in source and binary forms are permitted 6*35319Sbostic * provided that the above copyright notice and this paragraph are 7*35319Sbostic * duplicated in all such forms and that any documentation, 8*35319Sbostic * advertising materials, and other materials related to such 9*35319Sbostic * distribution and use acknowledge that the software was developed 10*35319Sbostic * by the University of California, Berkeley. The name of the 11*35319Sbostic * University may not be used to endorse or promote products derived 12*35319Sbostic * from this software without specific prior written permission. 13*35319Sbostic * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14*35319Sbostic * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15*35319Sbostic * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16*35319Sbostic * 17*35319Sbostic * @(#)if_enreg.h 7.2 (Berkeley) 08/04/88 1823291Smckusick */ 194765Swnj 204765Swnj /* 214765Swnj * Xerox experimental ethernet registers. 224765Swnj * 234765Swnj * N.B.: status register and device address are read/write, 244765Swnj * device address is read-only, rest are WRITE ONLY! 254765Swnj */ 264765Swnj struct endevice { 274765Swnj short en_owc; /* output word count (10 bits) */ 284765Swnj short en_oba; /* output buffer address */ 294765Swnj short en_ostat; /* output control and status */ 304765Swnj short en_odelay; /* output start delay, 25usec units */ 314765Swnj short en_iwc; /* input word count */ 324765Swnj short en_iba; /* input buffer address */ 334765Swnj short en_istat; /* input csr */ 344765Swnj short en_addr; /* ~device address (low 8 bits) */ 354765Swnj }; 364765Swnj 374765Swnj /* 384765Swnj * Control and status bits. 394765Swnj */ 404765Swnj #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ 414765Swnj #define EN_OERROR 0x8000 /* collision or output underrun */ 424765Swnj #define EN_OPDONE 0x0080 /* previous operation completed */ 434765Swnj #define EN_IEN 0x0040 /* enable interrupt when DONE */ 444772Swnj #define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */ 454765Swnj #define EN_GO 0x0001 /* start op bit */ 464765Swnj 474765Swnj #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" 484765Swnj 494765Swnj #define spl_enet() spl5() 50