123291Smckusick /* 229279Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 335319Sbostic * All rights reserved. 423291Smckusick * 5*44559Sbostic * %sccs.include.redist.c% 635319Sbostic * 7*44559Sbostic * @(#)if_enreg.h 7.3 (Berkeley) 06/28/90 823291Smckusick */ 94765Swnj 104765Swnj /* 114765Swnj * Xerox experimental ethernet registers. 124765Swnj * 134765Swnj * N.B.: status register and device address are read/write, 144765Swnj * device address is read-only, rest are WRITE ONLY! 154765Swnj */ 164765Swnj struct endevice { 174765Swnj short en_owc; /* output word count (10 bits) */ 184765Swnj short en_oba; /* output buffer address */ 194765Swnj short en_ostat; /* output control and status */ 204765Swnj short en_odelay; /* output start delay, 25usec units */ 214765Swnj short en_iwc; /* input word count */ 224765Swnj short en_iba; /* input buffer address */ 234765Swnj short en_istat; /* input csr */ 244765Swnj short en_addr; /* ~device address (low 8 bits) */ 254765Swnj }; 264765Swnj 274765Swnj /* 284765Swnj * Control and status bits. 294765Swnj */ 304765Swnj #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ 314765Swnj #define EN_OERROR 0x8000 /* collision or output underrun */ 324765Swnj #define EN_OPDONE 0x0080 /* previous operation completed */ 334765Swnj #define EN_IEN 0x0040 /* enable interrupt when DONE */ 344772Swnj #define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */ 354765Swnj #define EN_GO 0x0001 /* start op bit */ 364765Swnj 374765Swnj #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" 384765Swnj 394765Swnj #define spl_enet() spl5() 40