xref: /csrg-svn/sys/vax/if/if_ecreg.h (revision 7471)
1*7471Sfeldman /*	if_ecreg.h	4.3	82/07/21	*/
26521Sfeldman 
36521Sfeldman /*
46521Sfeldman  * 3Com Ethernet controller registers.
56521Sfeldman  */
66521Sfeldman struct ecdevice {
76521Sfeldman 	short	ec_rcr;		/* Receive Control Register */
86521Sfeldman 	short	ec_xcr;		/* Transmit Control Register */
96521Sfeldman };
106521Sfeldman 
116521Sfeldman /*
126521Sfeldman  * Control and status bits -- rcr
136521Sfeldman  */
146521Sfeldman #define	EC_SPIE		0x8000		/* set parity interrupt enable */
156521Sfeldman #define	EC_ASTEP	0x4000		/* increment address counter */
166521Sfeldman #define	EC_AROM		0x2000		/* 1: Use address ROM, 0: use RAM */
176521Sfeldman #define	EC_PE		0x2000		/* Parity error */
186521Sfeldman #define	EC_AWCLK	0x1000		/* address write clock bit */
196521Sfeldman #define	EC_PIE		0x1000		/* Parity interrupt enable (read) */
206521Sfeldman #define	EC_ADATA	0x0f00		/* address/filtering */
216521Sfeldman #define	EC_RDONE	0x0080		/* receive done */
22*7471Sfeldman #define	EC_MDISAB	0x0080		/* memory disable */
236521Sfeldman #define	EC_RINTEN	0x0040		/* receive interrupt enable */
246521Sfeldman #define	EC_RCLR		0x0020		/* clear RDONE bit */
256521Sfeldman #define	EC_RWBN		0x0010		/* submit buffer for receive */
266521Sfeldman #define	EC_RBN		0x000f		/* buffer number */
276521Sfeldman 
286521Sfeldman #define	EC_RBITS	"\10\16PE\15PIE\10RDONE\7RINTEN"
296521Sfeldman 
306521Sfeldman /*
316521Sfeldman  * Control and status bits -- xcr
326521Sfeldman  */
336521Sfeldman #define	EC_JAM		0x8000		/* collision dectected */
346521Sfeldman #define	EC_JINTEN	0x4000		/* collision interrupt enable */
356521Sfeldman #define	EC_JCLR		0x2000		/* clear collision detect */
366521Sfeldman #define	EC_UECLR	0x0100		/* reset controller */
376521Sfeldman #define	EC_XDONE	0x0080		/* transmit done */
386521Sfeldman #define	EC_XINTEN	0x0040		/* transmit interrupt enable */
396521Sfeldman #define	EC_XCLR		0x0020		/* clear XDONE bit */
406521Sfeldman #define	EC_XWBN		0x0010		/* submit buffer for transmit */
416521Sfeldman #define	EC_XBN		0x000f		/* buffer number */
426521Sfeldman 
436521Sfeldman #define	EC_XBITS	"\10\20JAM\17JINTEN\10XDONE\7XINTEN"
446521Sfeldman 
456521Sfeldman /*
466521Sfeldman  * Useful combinations
476521Sfeldman  */
486521Sfeldman #define	EC_READ		(EC_AROM|0x600|EC_RINTEN|EC_RWBN)
496521Sfeldman #define	EC_WRITE	(EC_JINTEN|EC_XINTEN|EC_XWBN)
507288Ssam #define	EC_CLEAR	(EC_JINTEN|EC_XINTEN|EC_JCLR)
516521Sfeldman 
526521Sfeldman /*
536521Sfeldman  * Buffer number definitions
546521Sfeldman  */
556521Sfeldman #define	ECTBF		0		/* Buffer for transmit */
566521Sfeldman #define	ECRLBF		1		/* First buffer for receive */
576521Sfeldman #define	ECRHBF		15		/* Last buffer for receive */
586521Sfeldman 
596521Sfeldman #define	ECRDOFF		528		/* Packet offset in read buffer */
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