1*7288Ssam /* if_ecreg.h 4.2 82/06/26 */ 26521Sfeldman 36521Sfeldman /* 46521Sfeldman * 3Com Ethernet controller registers. 56521Sfeldman */ 66521Sfeldman struct ecdevice { 76521Sfeldman short ec_rcr; /* Receive Control Register */ 86521Sfeldman short ec_xcr; /* Transmit Control Register */ 96521Sfeldman }; 106521Sfeldman 116521Sfeldman /* 126521Sfeldman * Control and status bits -- rcr 136521Sfeldman */ 146521Sfeldman #define EC_SPIE 0x8000 /* set parity interrupt enable */ 156521Sfeldman #define EC_ASTEP 0x4000 /* increment address counter */ 166521Sfeldman #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ 176521Sfeldman #define EC_PE 0x2000 /* Parity error */ 186521Sfeldman #define EC_AWCLK 0x1000 /* address write clock bit */ 196521Sfeldman #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ 206521Sfeldman #define EC_ADATA 0x0f00 /* address/filtering */ 216521Sfeldman #define EC_RDONE 0x0080 /* receive done */ 226521Sfeldman #define EC_RINTEN 0x0040 /* receive interrupt enable */ 236521Sfeldman #define EC_RCLR 0x0020 /* clear RDONE bit */ 246521Sfeldman #define EC_RWBN 0x0010 /* submit buffer for receive */ 256521Sfeldman #define EC_RBN 0x000f /* buffer number */ 266521Sfeldman 276521Sfeldman #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" 286521Sfeldman 296521Sfeldman /* 306521Sfeldman * Control and status bits -- xcr 316521Sfeldman */ 326521Sfeldman #define EC_JAM 0x8000 /* collision dectected */ 336521Sfeldman #define EC_JINTEN 0x4000 /* collision interrupt enable */ 346521Sfeldman #define EC_JCLR 0x2000 /* clear collision detect */ 356521Sfeldman #define EC_UECLR 0x0100 /* reset controller */ 366521Sfeldman #define EC_XDONE 0x0080 /* transmit done */ 376521Sfeldman #define EC_XINTEN 0x0040 /* transmit interrupt enable */ 386521Sfeldman #define EC_XCLR 0x0020 /* clear XDONE bit */ 396521Sfeldman #define EC_XWBN 0x0010 /* submit buffer for transmit */ 406521Sfeldman #define EC_XBN 0x000f /* buffer number */ 416521Sfeldman 426521Sfeldman #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" 436521Sfeldman 446521Sfeldman /* 456521Sfeldman * Useful combinations 466521Sfeldman */ 476521Sfeldman #define EC_READ (EC_AROM|0x600|EC_RINTEN|EC_RWBN) 486521Sfeldman #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) 49*7288Ssam #define EC_CLEAR (EC_JINTEN|EC_XINTEN|EC_JCLR) 506521Sfeldman 516521Sfeldman /* 526521Sfeldman * Buffer number definitions 536521Sfeldman */ 546521Sfeldman #define ECTBF 0 /* Buffer for transmit */ 556521Sfeldman #define ECRLBF 1 /* First buffer for receive */ 566521Sfeldman #define ECRHBF 15 /* Last buffer for receive */ 576521Sfeldman 586521Sfeldman #define ECRDOFF 528 /* Packet offset in read buffer */ 59