1*6521Sfeldman /* if_ecreg.h 4.1 82/04/11 */ 2*6521Sfeldman 3*6521Sfeldman /* 4*6521Sfeldman * 3Com Ethernet controller registers. 5*6521Sfeldman */ 6*6521Sfeldman struct ecdevice { 7*6521Sfeldman short ec_rcr; /* Receive Control Register */ 8*6521Sfeldman short ec_xcr; /* Transmit Control Register */ 9*6521Sfeldman }; 10*6521Sfeldman 11*6521Sfeldman /* 12*6521Sfeldman * Control and status bits -- rcr 13*6521Sfeldman */ 14*6521Sfeldman #define EC_SPIE 0x8000 /* set parity interrupt enable */ 15*6521Sfeldman #define EC_ASTEP 0x4000 /* increment address counter */ 16*6521Sfeldman #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ 17*6521Sfeldman #define EC_PE 0x2000 /* Parity error */ 18*6521Sfeldman #define EC_AWCLK 0x1000 /* address write clock bit */ 19*6521Sfeldman #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ 20*6521Sfeldman #define EC_ADATA 0x0f00 /* address/filtering */ 21*6521Sfeldman #define EC_RDONE 0x0080 /* receive done */ 22*6521Sfeldman #define EC_RINTEN 0x0040 /* receive interrupt enable */ 23*6521Sfeldman #define EC_RCLR 0x0020 /* clear RDONE bit */ 24*6521Sfeldman #define EC_RWBN 0x0010 /* submit buffer for receive */ 25*6521Sfeldman #define EC_RBN 0x000f /* buffer number */ 26*6521Sfeldman 27*6521Sfeldman #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" 28*6521Sfeldman 29*6521Sfeldman /* 30*6521Sfeldman * Control and status bits -- xcr 31*6521Sfeldman */ 32*6521Sfeldman #define EC_JAM 0x8000 /* collision dectected */ 33*6521Sfeldman #define EC_JINTEN 0x4000 /* collision interrupt enable */ 34*6521Sfeldman #define EC_JCLR 0x2000 /* clear collision detect */ 35*6521Sfeldman #define EC_UECLR 0x0100 /* reset controller */ 36*6521Sfeldman #define EC_XDONE 0x0080 /* transmit done */ 37*6521Sfeldman #define EC_XINTEN 0x0040 /* transmit interrupt enable */ 38*6521Sfeldman #define EC_XCLR 0x0020 /* clear XDONE bit */ 39*6521Sfeldman #define EC_XWBN 0x0010 /* submit buffer for transmit */ 40*6521Sfeldman #define EC_XBN 0x000f /* buffer number */ 41*6521Sfeldman 42*6521Sfeldman #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" 43*6521Sfeldman 44*6521Sfeldman /* 45*6521Sfeldman * Useful combinations 46*6521Sfeldman */ 47*6521Sfeldman #define EC_READ (EC_AROM|0x600|EC_RINTEN|EC_RWBN) 48*6521Sfeldman #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) 49*6521Sfeldman 50*6521Sfeldman /* 51*6521Sfeldman * Buffer number definitions 52*6521Sfeldman */ 53*6521Sfeldman #define ECTBF 0 /* Buffer for transmit */ 54*6521Sfeldman #define ECRLBF 1 /* First buffer for receive */ 55*6521Sfeldman #define ECRHBF 15 /* Last buffer for receive */ 56*6521Sfeldman 57*6521Sfeldman #define ECRDOFF 528 /* Packet offset in read buffer */ 58