123289Smckusick /* 229277Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 335318Sbostic * All rights reserved. 423289Smckusick * 535318Sbostic * Redistribution and use in source and binary forms are permitted 635318Sbostic * provided that the above copyright notice and this paragraph are 735318Sbostic * duplicated in all such forms and that any documentation, 835318Sbostic * advertising materials, and other materials related to such 935318Sbostic * distribution and use acknowledge that the software was developed 1035318Sbostic * by the University of California, Berkeley. The name of the 1135318Sbostic * University may not be used to endorse or promote products derived 1235318Sbostic * from this software without specific prior written permission. 1335318Sbostic * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 1435318Sbostic * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 1535318Sbostic * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 1635318Sbostic * 17*37476Ssklower * @(#)if_ecreg.h 7.3 (Berkeley) 04/22/89 1823289Smckusick */ 196521Sfeldman 206521Sfeldman /* 216521Sfeldman * 3Com Ethernet controller registers. 226521Sfeldman */ 236521Sfeldman struct ecdevice { 246521Sfeldman short ec_rcr; /* Receive Control Register */ 256521Sfeldman short ec_xcr; /* Transmit Control Register */ 266521Sfeldman }; 276521Sfeldman 286521Sfeldman /* 296521Sfeldman * Control and status bits -- rcr 306521Sfeldman */ 316521Sfeldman #define EC_SPIE 0x8000 /* set parity interrupt enable */ 326521Sfeldman #define EC_ASTEP 0x4000 /* increment address counter */ 336521Sfeldman #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ 346521Sfeldman #define EC_PE 0x2000 /* Parity error */ 356521Sfeldman #define EC_AWCLK 0x1000 /* address write clock bit */ 366521Sfeldman #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ 376521Sfeldman #define EC_ADATA 0x0f00 /* address/filtering */ 386521Sfeldman #define EC_RDONE 0x0080 /* receive done */ 397471Sfeldman #define EC_MDISAB 0x0080 /* memory disable */ 406521Sfeldman #define EC_RINTEN 0x0040 /* receive interrupt enable */ 416521Sfeldman #define EC_RCLR 0x0020 /* clear RDONE bit */ 426521Sfeldman #define EC_RWBN 0x0010 /* submit buffer for receive */ 436521Sfeldman #define EC_RBN 0x000f /* buffer number */ 446521Sfeldman 456521Sfeldman #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" 466521Sfeldman 476521Sfeldman /* 486521Sfeldman * Control and status bits -- xcr 496521Sfeldman */ 506521Sfeldman #define EC_JAM 0x8000 /* collision dectected */ 516521Sfeldman #define EC_JINTEN 0x4000 /* collision interrupt enable */ 526521Sfeldman #define EC_JCLR 0x2000 /* clear collision detect */ 536521Sfeldman #define EC_UECLR 0x0100 /* reset controller */ 546521Sfeldman #define EC_XDONE 0x0080 /* transmit done */ 556521Sfeldman #define EC_XINTEN 0x0040 /* transmit interrupt enable */ 566521Sfeldman #define EC_XCLR 0x0020 /* clear XDONE bit */ 576521Sfeldman #define EC_XWBN 0x0010 /* submit buffer for transmit */ 586521Sfeldman #define EC_XBN 0x000f /* buffer number */ 596521Sfeldman 606521Sfeldman #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" 616521Sfeldman 626521Sfeldman /* 636521Sfeldman * Useful combinations 646521Sfeldman */ 6523841Ssklower #define EC_READ (0x600|EC_RINTEN|EC_RWBN) 66*37476Ssklower #define EC_MULTI (0x700|EC_RINTEN|EC_RWBN) 67*37476Ssklower #define EC_PROMISC (0x000|EC_RINTEN|EC_RWBN) 686521Sfeldman #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) 697288Ssam #define EC_CLEAR (EC_JINTEN|EC_XINTEN|EC_JCLR) 706521Sfeldman 716521Sfeldman /* 726521Sfeldman * Buffer number definitions 736521Sfeldman */ 746521Sfeldman #define ECTBF 0 /* Buffer for transmit */ 756521Sfeldman #define ECRLBF 1 /* First buffer for receive */ 766521Sfeldman #define ECRHBF 15 /* Last buffer for receive */ 776521Sfeldman 786521Sfeldman #define ECRDOFF 528 /* Packet offset in read buffer */ 79