xref: /csrg-svn/sys/vax/if/if_ecreg.h (revision 44558)
123289Smckusick /*
229277Smckusick  * Copyright (c) 1982, 1986 Regents of the University of California.
335318Sbostic  * All rights reserved.
423289Smckusick  *
5*44558Sbostic  * %sccs.include.redist.c%
635318Sbostic  *
7*44558Sbostic  *	@(#)if_ecreg.h	7.4 (Berkeley) 06/28/90
823289Smckusick  */
96521Sfeldman 
106521Sfeldman /*
116521Sfeldman  * 3Com Ethernet controller registers.
126521Sfeldman  */
136521Sfeldman struct ecdevice {
146521Sfeldman 	short	ec_rcr;		/* Receive Control Register */
156521Sfeldman 	short	ec_xcr;		/* Transmit Control Register */
166521Sfeldman };
176521Sfeldman 
186521Sfeldman /*
196521Sfeldman  * Control and status bits -- rcr
206521Sfeldman  */
216521Sfeldman #define	EC_SPIE		0x8000		/* set parity interrupt enable */
226521Sfeldman #define	EC_ASTEP	0x4000		/* increment address counter */
236521Sfeldman #define	EC_AROM		0x2000		/* 1: Use address ROM, 0: use RAM */
246521Sfeldman #define	EC_PE		0x2000		/* Parity error */
256521Sfeldman #define	EC_AWCLK	0x1000		/* address write clock bit */
266521Sfeldman #define	EC_PIE		0x1000		/* Parity interrupt enable (read) */
276521Sfeldman #define	EC_ADATA	0x0f00		/* address/filtering */
286521Sfeldman #define	EC_RDONE	0x0080		/* receive done */
297471Sfeldman #define	EC_MDISAB	0x0080		/* memory disable */
306521Sfeldman #define	EC_RINTEN	0x0040		/* receive interrupt enable */
316521Sfeldman #define	EC_RCLR		0x0020		/* clear RDONE bit */
326521Sfeldman #define	EC_RWBN		0x0010		/* submit buffer for receive */
336521Sfeldman #define	EC_RBN		0x000f		/* buffer number */
346521Sfeldman 
356521Sfeldman #define	EC_RBITS	"\10\16PE\15PIE\10RDONE\7RINTEN"
366521Sfeldman 
376521Sfeldman /*
386521Sfeldman  * Control and status bits -- xcr
396521Sfeldman  */
406521Sfeldman #define	EC_JAM		0x8000		/* collision dectected */
416521Sfeldman #define	EC_JINTEN	0x4000		/* collision interrupt enable */
426521Sfeldman #define	EC_JCLR		0x2000		/* clear collision detect */
436521Sfeldman #define	EC_UECLR	0x0100		/* reset controller */
446521Sfeldman #define	EC_XDONE	0x0080		/* transmit done */
456521Sfeldman #define	EC_XINTEN	0x0040		/* transmit interrupt enable */
466521Sfeldman #define	EC_XCLR		0x0020		/* clear XDONE bit */
476521Sfeldman #define	EC_XWBN		0x0010		/* submit buffer for transmit */
486521Sfeldman #define	EC_XBN		0x000f		/* buffer number */
496521Sfeldman 
506521Sfeldman #define	EC_XBITS	"\10\20JAM\17JINTEN\10XDONE\7XINTEN"
516521Sfeldman 
526521Sfeldman /*
536521Sfeldman  * Useful combinations
546521Sfeldman  */
5523841Ssklower #define	EC_READ		(0x600|EC_RINTEN|EC_RWBN)
5637476Ssklower #define	EC_MULTI	(0x700|EC_RINTEN|EC_RWBN)
5737476Ssklower #define EC_PROMISC	(0x000|EC_RINTEN|EC_RWBN)
586521Sfeldman #define	EC_WRITE	(EC_JINTEN|EC_XINTEN|EC_XWBN)
597288Ssam #define	EC_CLEAR	(EC_JINTEN|EC_XINTEN|EC_JCLR)
606521Sfeldman 
616521Sfeldman /*
626521Sfeldman  * Buffer number definitions
636521Sfeldman  */
646521Sfeldman #define	ECTBF		0		/* Buffer for transmit */
656521Sfeldman #define	ECRLBF		1		/* First buffer for receive */
666521Sfeldman #define	ECRHBF		15		/* Last buffer for receive */
676521Sfeldman 
686521Sfeldman #define	ECRDOFF		528		/* Packet offset in read buffer */
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