1*5921Ssam /* if_dmc.h 4.2 82/02/21 */ 25854Sroot 35854Sroot /* 45854Sroot * DMC-11 Interface 55854Sroot */ 65854Sroot 75854Sroot struct dmcdevice { 85854Sroot union { 95854Sroot char b[8]; 105854Sroot short w[4]; 115854Sroot } un; 125854Sroot }; 135854Sroot 145854Sroot #define bsel0 un.b[0] 155854Sroot #define bsel1 un.b[1] 165854Sroot #define bsel2 un.b[2] 175854Sroot #define bsel3 un.b[3] 185854Sroot #define bsel4 un.b[4] 195854Sroot #define bsel5 un.b[5] 205854Sroot #define bsel6 un.b[6] 215854Sroot #define bsel7 un.b[7] 225854Sroot #define sel0 un.w[0] 235854Sroot #define sel2 un.w[1] 245854Sroot #define sel4 un.w[2] 255854Sroot #define sel6 un.w[3] 265854Sroot 275854Sroot #define DMCMTU (2048) 285854Sroot 29*5921Ssam #define RDYSCAN 16 /* loop delay for RDYI after RQI */ 305854Sroot 315854Sroot /* defines for bsel0 */ 325854Sroot #define DMC_BACCI 0 335854Sroot #define DMC_CNTLI 1 345854Sroot #define DMC_PERR 2 355854Sroot #define DMC_BASEI 3 365854Sroot #define DMC_WRITE 0 /* transmit block */ 375854Sroot #define DMC_READ 4 /* read block */ 385854Sroot #define DMC_RQI 0040 /* port request bit */ 395854Sroot #define DMC_IEI 0100 /* enable input interrupts */ 405854Sroot #define DMC_RDYI 0200 /* port ready */ 415854Sroot 425854Sroot /* defines for bsel1 */ 435854Sroot #define DMC_MCLR 0100 /* DMC11 Master Clear */ 445854Sroot #define DMC_RUN 0200 /* clock running */ 455854Sroot 465854Sroot /* defines for bsel2 */ 475854Sroot #define DMC_BACCO 0 485854Sroot #define DMC_CNTLO 1 495854Sroot #define DMC_OUX 0 /* transmit block */ 505854Sroot #define DMC_OUR 4 /* read block */ 515854Sroot #define DMC_IEO 0100 /* enable output interrupts */ 525854Sroot #define DMC_RDYO 0200 /* port available */ 535854Sroot 545854Sroot /* defines for CNTLI mode */ 555854Sroot #define DMC_HDPLX 02000 /* half duplex DDCMP operation */ 565854Sroot #define DMC_SEC 04000 /* half duplex secondary station */ 575854Sroot #define DMC_MAINT 00400 /* enter maintenance mode */ 585854Sroot 595854Sroot /* defines for BACCI/O and BASEI mode */ 605854Sroot #define DMC_XMEM 0140000 /* xmem bit position */ 615854Sroot #define DMC_CCOUNT 0037777 /* character count mask */ 625854Sroot #define DMC_RESUME 0002000 /* resume (BASEI only) */ 635854Sroot 645854Sroot /* defines for CNTLO */ 655854Sroot #define DMC_CNTMASK 01777 665854Sroot #define DMC_FATAL 01620 67