1*5854Sroot /* if_dmc.h 4.1 82/02/15 */ 2*5854Sroot 3*5854Sroot /* 4*5854Sroot * DMC-11 Interface 5*5854Sroot */ 6*5854Sroot 7*5854Sroot struct dmcdevice { 8*5854Sroot union { 9*5854Sroot char b[8]; 10*5854Sroot short w[4]; 11*5854Sroot } un; 12*5854Sroot }; 13*5854Sroot 14*5854Sroot #define bsel0 un.b[0] 15*5854Sroot #define bsel1 un.b[1] 16*5854Sroot #define bsel2 un.b[2] 17*5854Sroot #define bsel3 un.b[3] 18*5854Sroot #define bsel4 un.b[4] 19*5854Sroot #define bsel5 un.b[5] 20*5854Sroot #define bsel6 un.b[6] 21*5854Sroot #define bsel7 un.b[7] 22*5854Sroot #define sel0 un.w[0] 23*5854Sroot #define sel2 un.w[1] 24*5854Sroot #define sel4 un.w[2] 25*5854Sroot #define sel6 un.w[3] 26*5854Sroot 27*5854Sroot #define DMCMTU (2048) 28*5854Sroot 29*5854Sroot #define RDYSCAN 16 /* loop delay for RDYI after RQI */ 30*5854Sroot 31*5854Sroot /* defines for bsel0 */ 32*5854Sroot #define DMC_BACCI 0 33*5854Sroot #define DMC_CNTLI 1 34*5854Sroot #define DMC_PERR 2 35*5854Sroot #define DMC_BASEI 3 36*5854Sroot #define DMC_WRITE 0 /* transmit block */ 37*5854Sroot #define DMC_READ 4 /* read block */ 38*5854Sroot #define DMC_RQI 0040 /* port request bit */ 39*5854Sroot #define DMC_IEI 0100 /* enable input interrupts */ 40*5854Sroot #define DMC_RDYI 0200 /* port ready */ 41*5854Sroot 42*5854Sroot /* defines for bsel1 */ 43*5854Sroot #define DMC_MCLR 0100 /* DMC11 Master Clear */ 44*5854Sroot #define DMC_RUN 0200 /* clock running */ 45*5854Sroot 46*5854Sroot /* defines for bsel2 */ 47*5854Sroot #define DMC_BACCO 0 48*5854Sroot #define DMC_CNTLO 1 49*5854Sroot #define DMC_OUX 0 /* transmit block */ 50*5854Sroot #define DMC_OUR 4 /* read block */ 51*5854Sroot #define DMC_IEO 0100 /* enable output interrupts */ 52*5854Sroot #define DMC_RDYO 0200 /* port available */ 53*5854Sroot 54*5854Sroot /* defines for CNTLI mode */ 55*5854Sroot #define DMC_HDPLX 02000 /* half duplex DDCMP operation */ 56*5854Sroot #define DMC_SEC 04000 /* half duplex secondary station */ 57*5854Sroot #define DMC_MAINT 00400 /* enter maintenance mode */ 58*5854Sroot 59*5854Sroot /* defines for BACCI/O and BASEI mode */ 60*5854Sroot #define DMC_XMEM 0140000 /* xmem bit position */ 61*5854Sroot #define DMC_CCOUNT 0037777 /* character count mask */ 62*5854Sroot #define DMC_RESUME 0002000 /* resume (BASEI only) */ 63*5854Sroot 64*5854Sroot /* defines for CNTLO */ 65*5854Sroot #define DMC_CNTMASK 01777 66*5854Sroot #define DMC_FATAL 01620 67