xref: /csrg-svn/sys/vax/if/if_dmc.h (revision 17219)
1*17219Stef /*	if_dmc.h	6.2	84/09/26	*/
25854Sroot 
35854Sroot /*
45854Sroot  * DMC-11 Interface
55854Sroot  */
65854Sroot 
75854Sroot struct dmcdevice {
85854Sroot 	union {
95854Sroot 		char	b[8];
105854Sroot 		short	w[4];
115854Sroot 	} un;
125854Sroot };
135854Sroot 
145854Sroot #define	bsel0	un.b[0]
155854Sroot #define	bsel1	un.b[1]
165854Sroot #define	bsel2	un.b[2]
175854Sroot #define	bsel3	un.b[3]
185854Sroot #define	bsel4	un.b[4]
195854Sroot #define	bsel5	un.b[5]
205854Sroot #define	bsel6	un.b[6]
215854Sroot #define	bsel7	un.b[7]
225854Sroot #define	sel0	un.w[0]
235854Sroot #define	sel2	un.w[1]
245854Sroot #define	sel4	un.w[2]
255854Sroot #define	sel6	un.w[3]
265854Sroot 
27*17219Stef #define	DMCMTU	(1024)
285854Sroot 
295921Ssam #define	RDYSCAN	16	/* loop delay for RDYI after RQI */
305854Sroot 
315854Sroot /* defines for bsel0 */
325854Sroot #define	DMC_BACCI	0
335854Sroot #define	DMC_CNTLI	1
345854Sroot #define	DMC_PERR	2
355854Sroot #define	DMC_BASEI	3
365854Sroot #define	DMC_WRITE	0		/* transmit block */
375854Sroot #define	DMC_READ	4		/* read block */
385854Sroot #define	DMC_RQI		0040		/* port request bit */
395854Sroot #define	DMC_IEI		0100		/* enable input interrupts */
405854Sroot #define	DMC_RDYI	0200		/* port ready */
41*17219Stef #define	DMC0BITS	"\10\8RDI\7IEI\6RQI"
425854Sroot 
435854Sroot /* defines for bsel1 */
445854Sroot #define	DMC_MCLR	0100		/* DMC11 Master Clear */
455854Sroot #define	DMC_RUN		0200		/* clock running */
46*17219Stef #define	DMC1BITS	"\10\8RUN\7MCLR"
475854Sroot 
485854Sroot /* defines for bsel2 */
495854Sroot #define	DMC_BACCO	0
505854Sroot #define	DMC_CNTLO	1
515854Sroot #define	DMC_OUX		0		/* transmit block */
525854Sroot #define	DMC_OUR		4		/* read block */
535854Sroot #define	DMC_IEO		0100		/* enable output interrupts */
545854Sroot #define	DMC_RDYO	0200		/* port available */
55*17219Stef #define	DMC2BITS	"\10\8RDO\7IEO"
565854Sroot 
575854Sroot /* defines for CNTLI mode */
585854Sroot #define	DMC_HDPLX	02000		/* half duplex DDCMP operation */
595854Sroot #define	DMC_SEC		04000		/* half duplex secondary station */
605854Sroot #define	DMC_MAINT	00400		/* enter maintenance mode */
615854Sroot 
625854Sroot /* defines for BACCI/O and BASEI mode */
635854Sroot #define	DMC_XMEM	0140000		/* xmem bit position */
645854Sroot #define	DMC_CCOUNT	0037777		/* character count mask */
655854Sroot #define	DMC_RESUME	0002000		/* resume (BASEI only) */
665854Sroot 
675854Sroot /* defines for CNTLO */
685854Sroot #define	DMC_CNTMASK	01777
69*17219Stef 
70*17219Stef #define	DMC_DATACK	01
71*17219Stef #define	DMC_TIMEOUT	02
72*17219Stef #define	DMC_NOBUFS	04
73*17219Stef #define	DMC_MAINTREC	010
74*17219Stef #define	DMC_LOSTDATA	020
75*17219Stef #define	DMC_DISCONN	0100
76*17219Stef #define	DMC_START	0200
77*17219Stef #define	DMC_NEXMEM	0400
78*17219Stef #define	DMC_ERROR	01000
79*17219Stef 
80*17219Stef #define	DMC_FATAL (DMC_ERROR|DMC_NEXMEM|DMC_START|DMC_LOSTDATA|DMC_MAINTREC)
81*17219Stef #define	CNTLO_BITS	\
82*17219Stef    "\10\12ERROR\11NEXMEM\10START\7DISC\5LSTDATA\4MAINT\3NOBUF\2TIMEO\1DATACK"
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