xref: /csrg-svn/sys/vax/if/if_dmc.c (revision 6502)
1 /*	if_dmc.c	4.10	82/04/10	*/
2 
3 #include "dmc.h"
4 #if NDMC > 0
5 #define printd if(dmcdebug)printf
6 int dmcdebug = 1;
7 /*
8  * DMC11 device driver, internet version
9  *
10  * TODO
11  *	allow more than one outstanding read or write.
12  */
13 
14 #include "../h/param.h"
15 #include "../h/systm.h"
16 #include "../h/mbuf.h"
17 #include "../h/pte.h"
18 #include "../h/buf.h"
19 #include "../h/tty.h"
20 #include "../h/protosw.h"
21 #include "../h/socket.h"
22 #include "../h/ubareg.h"
23 #include "../h/ubavar.h"
24 #include "../h/cpu.h"
25 #include "../h/mtpr.h"
26 #include "../h/vmmac.h"
27 #include "../net/in.h"
28 #include "../net/in_systm.h"
29 #include "../net/if.h"
30 #include "../net/if_uba.h"
31 #include "../net/if_dmc.h"
32 #include "../net/ip.h"
33 #include "../net/ip_var.h"
34 #include "../net/route.h"
35 #include <errno.h>
36 
37 /*
38  * Driver information for auto-configuration stuff.
39  */
40 int	dmcprobe(), dmcattach(), dmcinit(), dmcoutput(), dmcreset();
41 struct	uba_device *dmcinfo[NDMC];
42 u_short	dmcstd[] = { 0 };
43 struct	uba_driver dmcdriver =
44 	{ dmcprobe, 0, dmcattach, 0, dmcstd, "dmc", dmcinfo };
45 
46 #define	DMC_AF	0xff		/* 8 bits of address type in ui_flags */
47 #define	DMC_NET	0xff00		/* 8 bits of net number in ui_flags */
48 
49 /*
50  * DMC software status per interface.
51  *
52  * Each interface is referenced by a network interface structure,
53  * sc_if, which the routing code uses to locate the interface.
54  * This structure contains the output queue for the interface, its address, ...
55  * We also have, for each interface, a UBA interface structure, which
56  * contains information about the UNIBUS resources held by the interface:
57  * map registers, buffered data paths, etc.  Information is cached in this
58  * structure for use by the if_uba.c routines in running the interface
59  * efficiently.
60  */
61 struct dmc_softc {
62 	struct	ifnet sc_if;		/* network-visible interface */
63 	struct	ifuba sc_ifuba;		/* UNIBUS resources */
64 	short	sc_flag;		/* flags */
65 	short	sc_oactive;		/* output active */
66 	int	sc_ubinfo;		/* UBA mapping info for base table */
67 	struct clist sc_que;		/* command queue */
68 } dmc_softc[NDMC];
69 
70 /* flags */
71 #define	DMCRUN		01
72 #define	DMCBMAPPED	02		/* base table mapped */
73 
74 struct dmc_base {
75 	short	d_base[128];		/* DMC base table */
76 } dmc_base[NDMC];
77 
78 #define	loword(x)	((short *)&x)[0]
79 #define	hiword(x)	((short *)&x)[1]
80 
81 dmcprobe(reg)
82 	caddr_t reg;
83 {
84 	register int br, cvec;
85 	register struct dmcdevice *addr = (struct dmcdevice *)reg;
86 	register int i;
87 
88 COUNT(DMCPROBE);
89 #ifdef lint
90 	br = 0; cvec = br; br = cvec;
91 	dmcrint(0); dmcxint(0);
92 #endif
93 	addr->bsel1 = DMC_MCLR;
94 	for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--)
95 		;
96 	if ((addr->bsel1 & DMC_RUN) == 0)
97 		return (0);
98 	addr->bsel1 &= ~DMC_MCLR;
99 	addr->bsel0 = DMC_RQI|DMC_IEI;
100 	DELAY(100000);
101 	addr->bsel1 = DMC_MCLR;
102 	for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--)
103 		;
104 	return (1);
105 }
106 
107 /*
108  * Interface exists: make available by filling in network interface
109  * record.  System will initialize the interface when it is ready
110  * to accept packets.
111  */
112 dmcattach(ui)
113 	register struct uba_device *ui;
114 {
115 	register struct dmc_softc *sc = &dmc_softc[ui->ui_unit];
116 	register struct sockaddr_in *sin;
117 
118 COUNT(DMCATTACH);
119 	sc->sc_if.if_unit = ui->ui_unit;
120 	sc->sc_if.if_name = "dmc";
121 	sc->sc_if.if_mtu = DMCMTU;
122 	sc->sc_if.if_net = (ui->ui_flags & DMC_NET) >> 8;
123 	sc->sc_if.if_host[0] = 17;	/* random number */
124 	sin = (struct sockaddr_in *)&sc->sc_if.if_addr;
125 	sin->sa_family = AF_INET;
126 	sin->sin_addr = if_makeaddr(sc->sc_if.if_net, sc->sc_if.if_host[0]);
127 	sc->sc_if.if_init = dmcinit;
128 	sc->sc_if.if_output = dmcoutput;
129 	sc->sc_if.if_ubareset = dmcreset;
130 	sc->sc_ifuba.ifuba_flags = UBA_NEEDBDP;
131 	if_attach(&sc->sc_if);
132 }
133 
134 /*
135  * Reset of interface after UNIBUS reset.
136  * If interface is on specified UBA, reset it's state.
137  */
138 dmcreset(unit, uban)
139 	int unit, uban;
140 {
141 	register struct uba_device *ui;
142 
143 COUNT(DMCRESET);
144 	if (unit >= NDMC || (ui = dmcinfo[unit]) == 0 || ui->ui_alive == 0 ||
145 	    ui->ui_ubanum != uban)
146 		return;
147 	printf(" dmc%d", unit);
148 	dmcinit(unit);
149 }
150 
151 /*
152  * Initialization of interface; reinitialize UNIBUS usage.
153  */
154 dmcinit(unit)
155 	int unit;
156 {
157 	register struct dmc_softc *sc = &dmc_softc[unit];
158 	register struct uba_device *ui = dmcinfo[unit];
159 	register struct dmcdevice *addr;
160 	int base;
161 
162 COUNT(DMCINIT);
163 	printd("dmcinit\n");
164 	if ((sc->sc_flag&DMCBMAPPED) == 0) {
165 		sc->sc_ubinfo = uballoc(ui->ui_ubanum,
166 		    (caddr_t)&dmc_base[unit], sizeof (struct dmc_base), 0);
167 		sc->sc_flag |= DMCBMAPPED;
168 	}
169 	if (if_ubainit(&sc->sc_ifuba, ui->ui_ubanum, 0,
170 	    (int)btoc(DMCMTU)) == 0) {
171 		printf("dmc%d: can't initialize\n", unit);
172 		sc->sc_if.if_flags &= ~IFF_UP;
173 		return;
174 	}
175 	addr = (struct dmcdevice *)ui->ui_addr;
176 	addr->bsel2 |= DMC_IEO;
177 	base = sc->sc_ubinfo & 0x3ffff;
178 	printd("  base 0x%x\n", base);
179 	dmcload(sc, DMC_BASEI, base, (base>>2)&DMC_XMEM);
180 	dmcload(sc, DMC_CNTLI, 0, 0);
181 	base = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff;
182 	dmcload(sc, DMC_READ, base, ((base>>2)&DMC_XMEM)|DMCMTU);
183 	printd("  first read queued, addr 0x%x\n", base);
184 	sc->sc_if.if_flags |= IFF_UP;
185 	/* set up routing table entry */
186 	if ((sc->sc_if.if_flags & IFF_ROUTE) == 0) {
187 		rtinit(&sc->sc_if.if_addr, &sc->sc_if.if_addr,
188 			RTF_DIRECT|RTF_HOST|RTF_UP);
189 		sc->sc_if.if_flags |= IFF_ROUTE;
190 	}
191 }
192 
193 /*
194  * Start output on interface.  Get another datagram
195  * to send from the interface queue and map it to
196  * the interface before starting output.
197  */
198 dmcstart(dev)
199 	dev_t dev;
200 {
201 	int unit = minor(dev);
202 	struct uba_device *ui = dmcinfo[unit];
203 	register struct dmc_softc *sc = &dmc_softc[unit];
204 	int addr, len;
205 	struct mbuf *m;
206 
207 COUNT(DMCSTART);
208 	printd("dmcstart\n");
209 	/*
210 	 * Dequeue a request and map it to the UNIBUS.
211 	 * If no more requests, just return.
212 	 */
213 	IF_DEQUEUE(&sc->sc_if.if_snd, m);
214 	if (m == 0)
215 		return;
216 	len = if_wubaput(&sc->sc_ifuba, m);
217 
218 	/*
219 	 * Have request mapped to UNIBUS for transmission.
220 	 * Purge any stale data from this BDP and start the output.
221 	 */
222 	if (sc->sc_ifuba.ifuba_flags & UBA_NEEDBDP)
223 		UBAPURGE(sc->sc_ifuba.ifu_uba, sc->sc_ifuba.ifu_w.ifrw_bdp);
224 	addr = sc->sc_ifuba.ifu_w.ifrw_info & 0x3ffff;
225 	printd("  len %d, addr 0x%x, ", len, addr);
226 	printd("mr 0x%x\n", sc->sc_ifuba.ifu_w.ifrw_mr[0]);
227 	dmcload(sc, DMC_WRITE, addr, (len&DMC_CCOUNT)|((addr>>2)&DMC_XMEM));
228 	sc->sc_oactive = 1;
229 }
230 
231 /*
232  * Utility routine to load the DMC device registers.
233  */
234 dmcload(sc, type, w0, w1)
235 	register struct dmc_softc *sc;
236 	int type, w0, w1;
237 {
238 	register struct dmcdevice *addr;
239 	register int unit, sps, n;
240 
241 COUNT(DMCLOAD);
242 	printd("dmcload: 0x%x 0x%x 0x%x\n", type, w0, w1);
243 	unit = sc - dmc_softc;
244 	addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr;
245 	sps = spl5();
246 	if ((n = sc->sc_que.c_cc) == 0)
247 		addr->bsel0 = type | DMC_RQI;
248 	else
249 		(void) putc(type | DMC_RQI, &sc->sc_que);
250 	(void) putw(w0, &sc->sc_que);
251 	(void) putw(w1, &sc->sc_que);
252 	if (n == 0)
253 		dmcrint(unit);
254 	splx(sps);
255 }
256 
257 /*
258  * DMC interface receiver interrupt.
259  * Ready to accept another command,
260  * pull one off the command queue.
261  */
262 dmcrint(unit)
263 	int unit;
264 {
265 	register struct dmc_softc *sc;
266 	register struct dmcdevice *addr;
267 	register int n;
268 	int w0, w1; /* DEBUG */
269 
270 COUNT(DMCRINT);
271 	addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr;
272 	sc = &dmc_softc[unit];
273 	while (addr->bsel0&DMC_RDYI) {
274 		w0 = getw(&sc->sc_que); /* DEBUG */
275 		addr->sel4 = w0; /* DEBUG */
276 		w1 = getw(&sc->sc_que); /* DEBUG */
277 		addr->sel6 = w1; /* DEBUG */
278 		/* DEBUG
279 		addr->sel4 = getw(&sc->sc_que);
280 		addr->sel6 = getw(&sc->sc_que);
281 		DEBUG */
282 		addr->bsel0 &= ~(DMC_IEI|DMC_RQI);
283 		printd("  w0 0x%x, w1 0x%x\n", w0, w1);
284 		while (addr->bsel0&DMC_RDYI)
285 			;
286 		if (sc->sc_que.c_cc == 0)
287 			return;
288 		addr->bsel0 = getc(&sc->sc_que);
289 		n = RDYSCAN;
290 		while (n-- && (addr->bsel0&DMC_RDYI) == 0)
291 			;
292 	}
293 	if (sc->sc_que.c_cc)
294 		addr->bsel0 |= DMC_IEI;
295 }
296 
297 /*
298  * DMC interface transmitter interrupt.
299  * A transfer has completed, check for errors.
300  * If it was a read, notify appropriate protocol.
301  * If it was a write, pull the next one off the queue.
302  */
303 dmcxint(unit)
304 	int unit;
305 {
306 	register struct dmc_softc *sc;
307 	struct uba_device *ui = dmcinfo[unit];
308 	struct dmcdevice *addr;
309 	struct mbuf *m;
310 	register struct ifqueue *inq;
311 	int arg, cmd, len;
312 
313 COUNT(DMCXINT);
314 	addr = (struct dmcdevice *)ui->ui_addr;
315 	arg = addr->sel6;
316 	cmd = addr->bsel2&7;
317 	addr->bsel2 &= ~DMC_RDYO;
318 	sc = &dmc_softc[unit];
319 	printd("dmcxint\n");
320 	switch (cmd) {
321 
322 	case DMC_OUR:
323 		/*
324 		 * A read has completed.  Purge input buffered
325 		 * data path.  Pass packet to type specific
326 		 * higher-level input routine.
327 		 */
328 		sc->sc_if.if_ipackets++;
329 		if (sc->sc_ifuba.ifuba_flags & UBA_NEEDBDP)
330 			UBAPURGE(sc->sc_ifuba.ifu_uba,
331 				sc->sc_ifuba.ifu_r.ifrw_bdp);
332 		len = arg & DMC_CCOUNT;
333 		printd("  read done, len %d\n", len);
334 		switch (ui->ui_flags & DMC_AF) {
335 #ifdef INET
336 		case AF_INET:
337 			schednetisr(NETISR_IP);
338 			inq = &ipintrq;
339 			break;
340 #endif
341 
342 		default:
343 			printf("dmc%d: unknown address type %d\n", unit,
344 			    ui->ui_flags & DMC_AF);
345 			goto setup;
346 		}
347 		m = if_rubaget(&sc->sc_ifuba, len, 0);
348 		if (m == 0)
349 			goto setup;
350 		if (IF_QFULL(inq)) {
351 			IF_DROP(inq);
352 			(void) m_freem(m);
353 		} else
354 			IF_ENQUEUE(inq, m);
355 
356 setup:
357 		arg = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff;
358 		dmcload(sc, DMC_READ, arg, ((arg >> 2) & DMC_XMEM) | DMCMTU);
359 		return;
360 
361 	case DMC_OUX:
362 		/*
363 		 * A write has completed, start another
364 		 * transfer if there is more data to send.
365 		 */
366 		if (sc->sc_oactive == 0)
367 			return;		/* SHOULD IT BE A FATAL ERROR? */
368 		printd("  write done\n");
369 		sc->sc_if.if_opackets++;
370 		sc->sc_oactive = 0;
371 		if (sc->sc_ifuba.ifu_xtofree) {
372 			(void) m_freem(sc->sc_ifuba.ifu_xtofree);
373 			sc->sc_ifuba.ifu_xtofree = 0;
374 		}
375 		if (sc->sc_if.if_snd.ifq_head == 0)
376 			return;
377 		dmcstart(unit);
378 		return;
379 
380 	case DMC_CNTLO:
381 		arg &= DMC_CNTMASK;
382 		if (arg&DMC_FATAL) {
383 			addr->bsel1 = DMC_MCLR;
384 			sc->sc_flag &= ~DMCRUN;
385 			/*** DO SOMETHING TO RESTART DEVICE ***/
386 			printf("DMC FATAL ERROR 0%o\n", arg);
387 		} else {
388 			/* ACCUMULATE STATISTICS */
389 			printf("DMC SOFT ERROR 0%o\n", arg);
390 		}
391 		return;
392 
393 	default:
394 		printf("dmc%d: bad control %o\n", unit, cmd);
395 	}
396 }
397 
398 /*
399  * DMC output routine.
400  * Just send the data, header was supplied by
401  * upper level protocol routines.
402  */
403 dmcoutput(ifp, m, dst)
404 	register struct ifnet *ifp;
405 	register struct mbuf *m;
406 	struct sockaddr *dst;
407 {
408 	struct uba_device *ui = dmcinfo[ifp->if_unit];
409 	int s;
410 
411 COUNT(DMCOUTPUT);
412 	printd("dmcoutput\n");
413 	if (dst->sa_family != (ui->ui_flags & DMC_AF)) {
414 		printf("dmc%d: af%d not supported\n", ifp->if_unit, pf);
415 		m_freem(m);
416 		return (EAFNOSUPPORT);
417 	}
418 	s = splimp();
419 	if (IF_QFULL(&ifp->if_snd)) {
420 		IF_DROP(&ifp->if_snd);
421 		m_freem(m);
422 		splx(s);
423 		return (ENOBUFS);
424 	}
425 	IF_ENQUEUE(&ifp->if_snd, m);
426 	if (dmc_softc[ifp->if_unit].sc_oactive == 0)
427 		dmcstart(ifp->if_unit);
428 	splx(s);
429 	return (0);
430 }
431