1*11189Ssam /* if_dmc.c 4.23 83/02/20 */ 25725Sroot 35725Sroot #include "dmc.h" 45725Sroot #if NDMC > 0 55725Sroot #define printd if(dmcdebug)printf 6*11189Ssam int dmcdebug = 0; 75725Sroot /* 85725Sroot * DMC11 device driver, internet version 95725Sroot * 105725Sroot * TODO 115725Sroot * allow more than one outstanding read or write. 125725Sroot */ 139794Ssam #include "../machine/pte.h" 145725Sroot 155725Sroot #include "../h/param.h" 165725Sroot #include "../h/systm.h" 175725Sroot #include "../h/mbuf.h" 185725Sroot #include "../h/buf.h" 195725Sroot #include "../h/tty.h" 205725Sroot #include "../h/protosw.h" 215725Sroot #include "../h/socket.h" 225725Sroot #include "../h/vmmac.h" 238460Sroot #include <errno.h> 248460Sroot 258460Sroot #include "../net/if.h" 269176Ssam #include "../net/netisr.h" 278460Sroot #include "../net/route.h" 288416Swnj #include "../netinet/in.h" 298416Swnj #include "../netinet/in_systm.h" 308460Sroot 318460Sroot #include "../vax/cpu.h" 328460Sroot #include "../vax/mtpr.h" 338416Swnj #include "../vaxif/if_uba.h" 348416Swnj #include "../vaxif/if_dmc.h" 358460Sroot #include "../vaxuba/ubareg.h" 368460Sroot #include "../vaxuba/ubavar.h" 375725Sroot 38*11189Ssam #ifndef DMC_USEMAINT 39*11189Ssam #define DMC_USEMAINT 1 /* use maintenance mode */ 40*11189Ssam #endif 41*11189Ssam 425725Sroot /* 435725Sroot * Driver information for auto-configuration stuff. 445725Sroot */ 455725Sroot int dmcprobe(), dmcattach(), dmcinit(), dmcoutput(), dmcreset(); 465725Sroot struct uba_device *dmcinfo[NDMC]; 475725Sroot u_short dmcstd[] = { 0 }; 485725Sroot struct uba_driver dmcdriver = 495725Sroot { dmcprobe, 0, dmcattach, 0, dmcstd, "dmc", dmcinfo }; 505725Sroot 516334Ssam #define DMC_AF 0xff /* 8 bits of address type in ui_flags */ 527161Ssam #define DMC_NET 0xffffff00 /* 24 bits of net number in ui_flags */ 535725Sroot 545725Sroot /* 555725Sroot * DMC software status per interface. 565725Sroot * 575725Sroot * Each interface is referenced by a network interface structure, 585725Sroot * sc_if, which the routing code uses to locate the interface. 595725Sroot * This structure contains the output queue for the interface, its address, ... 605725Sroot * We also have, for each interface, a UBA interface structure, which 615725Sroot * contains information about the UNIBUS resources held by the interface: 625725Sroot * map registers, buffered data paths, etc. Information is cached in this 635725Sroot * structure for use by the if_uba.c routines in running the interface 645725Sroot * efficiently. 655725Sroot */ 665725Sroot struct dmc_softc { 675725Sroot struct ifnet sc_if; /* network-visible interface */ 685725Sroot struct ifuba sc_ifuba; /* UNIBUS resources */ 695725Sroot short sc_flag; /* flags */ 705725Sroot short sc_oactive; /* output active */ 715725Sroot int sc_ubinfo; /* UBA mapping info for base table */ 725725Sroot struct clist sc_que; /* command queue */ 735725Sroot } dmc_softc[NDMC]; 745725Sroot 755725Sroot /* flags */ 765725Sroot #define DMCRUN 01 775725Sroot #define DMCBMAPPED 02 /* base table mapped */ 785725Sroot 795725Sroot struct dmc_base { 805725Sroot short d_base[128]; /* DMC base table */ 815725Sroot } dmc_base[NDMC]; 825725Sroot 835725Sroot #define loword(x) ((short *)&x)[0] 845725Sroot #define hiword(x) ((short *)&x)[1] 855725Sroot 865725Sroot dmcprobe(reg) 875725Sroot caddr_t reg; 885725Sroot { 895725Sroot register int br, cvec; 905725Sroot register struct dmcdevice *addr = (struct dmcdevice *)reg; 915725Sroot register int i; 925725Sroot 935725Sroot #ifdef lint 945725Sroot br = 0; cvec = br; br = cvec; 955725Sroot dmcrint(0); dmcxint(0); 965725Sroot #endif 975725Sroot addr->bsel1 = DMC_MCLR; 985725Sroot for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--) 995725Sroot ; 1005725Sroot if ((addr->bsel1 & DMC_RUN) == 0) 1016334Ssam return (0); 1025725Sroot addr->bsel1 &= ~DMC_MCLR; 1035725Sroot addr->bsel0 = DMC_RQI|DMC_IEI; 1045725Sroot DELAY(100000); 1055725Sroot addr->bsel1 = DMC_MCLR; 1065725Sroot for (i = 100000; i && (addr->bsel1 & DMC_RUN) == 0; i--) 1075725Sroot ; 1086575Ssam #ifdef ECHACK 1096575Ssam br = 0x16; 1106575Ssam #endif 1116334Ssam return (1); 1125725Sroot } 1135725Sroot 1145725Sroot /* 1155725Sroot * Interface exists: make available by filling in network interface 1165725Sroot * record. System will initialize the interface when it is ready 1175725Sroot * to accept packets. 1185725Sroot */ 1195725Sroot dmcattach(ui) 1205725Sroot register struct uba_device *ui; 1215725Sroot { 1225725Sroot register struct dmc_softc *sc = &dmc_softc[ui->ui_unit]; 1236334Ssam register struct sockaddr_in *sin; 1245725Sroot 1255725Sroot sc->sc_if.if_unit = ui->ui_unit; 1265725Sroot sc->sc_if.if_name = "dmc"; 1275725Sroot sc->sc_if.if_mtu = DMCMTU; 1285725Sroot sc->sc_if.if_net = (ui->ui_flags & DMC_NET) >> 8; 1295725Sroot sc->sc_if.if_host[0] = 17; /* random number */ 1306334Ssam sin = (struct sockaddr_in *)&sc->sc_if.if_addr; 1316587Ssam sin->sin_family = AF_INET; 1326334Ssam sin->sin_addr = if_makeaddr(sc->sc_if.if_net, sc->sc_if.if_host[0]); 1335725Sroot sc->sc_if.if_init = dmcinit; 1345725Sroot sc->sc_if.if_output = dmcoutput; 1358976Sroot sc->sc_if.if_reset = dmcreset; 1366587Ssam /* DON'T KNOW IF THIS WILL WORK WITH A BDP AT HIGH SPEEDS */ 1376587Ssam sc->sc_ifuba.ifu_flags = UBA_NEEDBDP | UBA_CANTWAIT; 1385725Sroot if_attach(&sc->sc_if); 1395725Sroot } 1405725Sroot 1415725Sroot /* 1425725Sroot * Reset of interface after UNIBUS reset. 1435725Sroot * If interface is on specified UBA, reset it's state. 1445725Sroot */ 1455725Sroot dmcreset(unit, uban) 1465725Sroot int unit, uban; 1475725Sroot { 1485725Sroot register struct uba_device *ui; 1495725Sroot 1505725Sroot if (unit >= NDMC || (ui = dmcinfo[unit]) == 0 || ui->ui_alive == 0 || 1515725Sroot ui->ui_ubanum != uban) 1525725Sroot return; 1535725Sroot printf(" dmc%d", unit); 1545725Sroot dmcinit(unit); 1555725Sroot } 1565725Sroot 1575725Sroot /* 1585725Sroot * Initialization of interface; reinitialize UNIBUS usage. 1595725Sroot */ 1605725Sroot dmcinit(unit) 1615725Sroot int unit; 1625725Sroot { 1635725Sroot register struct dmc_softc *sc = &dmc_softc[unit]; 1645725Sroot register struct uba_device *ui = dmcinfo[unit]; 1655725Sroot register struct dmcdevice *addr; 1665725Sroot int base; 1675725Sroot 1685725Sroot printd("dmcinit\n"); 1695725Sroot if ((sc->sc_flag&DMCBMAPPED) == 0) { 1705725Sroot sc->sc_ubinfo = uballoc(ui->ui_ubanum, 1715725Sroot (caddr_t)&dmc_base[unit], sizeof (struct dmc_base), 0); 1725725Sroot sc->sc_flag |= DMCBMAPPED; 1735725Sroot } 1745725Sroot if (if_ubainit(&sc->sc_ifuba, ui->ui_ubanum, 0, 1755768Sroot (int)btoc(DMCMTU)) == 0) { 1765725Sroot printf("dmc%d: can't initialize\n", unit); 1776334Ssam sc->sc_if.if_flags &= ~IFF_UP; 1785725Sroot return; 1795725Sroot } 1805725Sroot addr = (struct dmcdevice *)ui->ui_addr; 1815725Sroot addr->bsel2 |= DMC_IEO; 1825725Sroot base = sc->sc_ubinfo & 0x3ffff; 1835725Sroot printd(" base 0x%x\n", base); 1845725Sroot dmcload(sc, DMC_BASEI, base, (base>>2)&DMC_XMEM); 185*11189Ssam dmcload(sc, DMC_CNTLI, 0, DMC_USEMAINT ? DMC_MAINT : 0); 1865725Sroot base = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff; 1875725Sroot dmcload(sc, DMC_READ, base, ((base>>2)&DMC_XMEM)|DMCMTU); 1885725Sroot printd(" first read queued, addr 0x%x\n", base); 1896334Ssam sc->sc_if.if_flags |= IFF_UP; 1906363Ssam /* set up routing table entry */ 1916363Ssam if ((sc->sc_if.if_flags & IFF_ROUTE) == 0) { 1927150Swnj rtinit(&sc->sc_if.if_addr, &sc->sc_if.if_addr, RTF_HOST|RTF_UP); 1936363Ssam sc->sc_if.if_flags |= IFF_ROUTE; 1946363Ssam } 1955725Sroot } 1965725Sroot 1975725Sroot /* 1985725Sroot * Start output on interface. Get another datagram 1995725Sroot * to send from the interface queue and map it to 2005725Sroot * the interface before starting output. 2015725Sroot */ 2025725Sroot dmcstart(dev) 2035725Sroot dev_t dev; 2045725Sroot { 2055725Sroot int unit = minor(dev); 2065725Sroot struct uba_device *ui = dmcinfo[unit]; 2075725Sroot register struct dmc_softc *sc = &dmc_softc[unit]; 2085725Sroot int addr, len; 2095725Sroot struct mbuf *m; 2105725Sroot 2115725Sroot printd("dmcstart\n"); 2125725Sroot /* 2135725Sroot * Dequeue a request and map it to the UNIBUS. 2145725Sroot * If no more requests, just return. 2155725Sroot */ 2165725Sroot IF_DEQUEUE(&sc->sc_if.if_snd, m); 2175725Sroot if (m == 0) 2185725Sroot return; 2195725Sroot len = if_wubaput(&sc->sc_ifuba, m); 2205725Sroot 2215725Sroot /* 2225725Sroot * Have request mapped to UNIBUS for transmission. 2235725Sroot * Purge any stale data from this BDP and start the output. 2245725Sroot */ 2256587Ssam if (sc->sc_ifuba.ifu_flags & UBA_NEEDBDP) 2265853Sroot UBAPURGE(sc->sc_ifuba.ifu_uba, sc->sc_ifuba.ifu_w.ifrw_bdp); 2275725Sroot addr = sc->sc_ifuba.ifu_w.ifrw_info & 0x3ffff; 2285725Sroot printd(" len %d, addr 0x%x, ", len, addr); 2295725Sroot printd("mr 0x%x\n", sc->sc_ifuba.ifu_w.ifrw_mr[0]); 2305725Sroot dmcload(sc, DMC_WRITE, addr, (len&DMC_CCOUNT)|((addr>>2)&DMC_XMEM)); 2315725Sroot sc->sc_oactive = 1; 2325725Sroot } 2335725Sroot 2345725Sroot /* 2355725Sroot * Utility routine to load the DMC device registers. 2365725Sroot */ 2375725Sroot dmcload(sc, type, w0, w1) 2385725Sroot register struct dmc_softc *sc; 2395725Sroot int type, w0, w1; 2405725Sroot { 2415725Sroot register struct dmcdevice *addr; 2425725Sroot register int unit, sps, n; 2435725Sroot 2445725Sroot printd("dmcload: 0x%x 0x%x 0x%x\n", type, w0, w1); 2455725Sroot unit = sc - dmc_softc; 2465725Sroot addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr; 2475725Sroot sps = spl5(); 2485725Sroot if ((n = sc->sc_que.c_cc) == 0) 2495725Sroot addr->bsel0 = type | DMC_RQI; 2505725Sroot else 2516159Ssam (void) putc(type | DMC_RQI, &sc->sc_que); 2526159Ssam (void) putw(w0, &sc->sc_que); 2536159Ssam (void) putw(w1, &sc->sc_que); 2545725Sroot if (n == 0) 2555725Sroot dmcrint(unit); 2565725Sroot splx(sps); 2575725Sroot } 2585725Sroot 2595725Sroot /* 2605725Sroot * DMC interface receiver interrupt. 2615725Sroot * Ready to accept another command, 2625725Sroot * pull one off the command queue. 2635725Sroot */ 2645725Sroot dmcrint(unit) 2655725Sroot int unit; 2665725Sroot { 2675725Sroot register struct dmc_softc *sc; 2685725Sroot register struct dmcdevice *addr; 2695725Sroot register int n; 2705725Sroot 2715725Sroot addr = (struct dmcdevice *)dmcinfo[unit]->ui_addr; 2725725Sroot sc = &dmc_softc[unit]; 2735725Sroot while (addr->bsel0&DMC_RDYI) { 2745725Sroot addr->sel4 = getw(&sc->sc_que); 2755725Sroot addr->sel6 = getw(&sc->sc_que); 2765725Sroot addr->bsel0 &= ~(DMC_IEI|DMC_RQI); 2775725Sroot while (addr->bsel0&DMC_RDYI) 2785725Sroot ; 2795725Sroot if (sc->sc_que.c_cc == 0) 280*11189Ssam goto out; 2815725Sroot addr->bsel0 = getc(&sc->sc_que); 2825725Sroot n = RDYSCAN; 2835725Sroot while (n-- && (addr->bsel0&DMC_RDYI) == 0) 2845725Sroot ; 2855725Sroot } 2865725Sroot if (sc->sc_que.c_cc) 2875725Sroot addr->bsel0 |= DMC_IEI; 288*11189Ssam out: 289*11189Ssam dmxint(unit); 2905725Sroot } 2915725Sroot 2925725Sroot /* 2935725Sroot * DMC interface transmitter interrupt. 2945725Sroot * A transfer has completed, check for errors. 2955725Sroot * If it was a read, notify appropriate protocol. 2965725Sroot * If it was a write, pull the next one off the queue. 2975725Sroot */ 2985725Sroot dmcxint(unit) 2995725Sroot int unit; 3005725Sroot { 3015725Sroot register struct dmc_softc *sc; 3025725Sroot struct uba_device *ui = dmcinfo[unit]; 3035725Sroot struct dmcdevice *addr; 3045725Sroot struct mbuf *m; 3055725Sroot register struct ifqueue *inq; 306*11189Ssam int arg, arg2, cmd, len; 3075725Sroot 3085725Sroot addr = (struct dmcdevice *)ui->ui_addr; 309*11189Ssam cmd = addr->bsel2 & 0xff; 310*11189Ssam if ((cmd & DMC_RDYO) == 0) 311*11189Ssam return; 312*11189Ssam arg2 = addr->sel4; 3135725Sroot arg = addr->sel6; 3145725Sroot addr->bsel2 &= ~DMC_RDYO; 3155725Sroot sc = &dmc_softc[unit]; 3165725Sroot printd("dmcxint\n"); 317*11189Ssam switch (cmd & 07) { 3185725Sroot 3195725Sroot case DMC_OUR: 3205725Sroot /* 3215725Sroot * A read has completed. Purge input buffered 3225725Sroot * data path. Pass packet to type specific 3235725Sroot * higher-level input routine. 3245725Sroot */ 3255725Sroot sc->sc_if.if_ipackets++; 3266587Ssam if (sc->sc_ifuba.ifu_flags & UBA_NEEDBDP) 3275853Sroot UBAPURGE(sc->sc_ifuba.ifu_uba, 3285853Sroot sc->sc_ifuba.ifu_r.ifrw_bdp); 3295725Sroot len = arg & DMC_CCOUNT; 3305725Sroot printd(" read done, len %d\n", len); 3316334Ssam switch (ui->ui_flags & DMC_AF) { 3325725Sroot #ifdef INET 3336334Ssam case AF_INET: 3346260Swnj schednetisr(NETISR_IP); 3355725Sroot inq = &ipintrq; 3365725Sroot break; 3375725Sroot #endif 3385725Sroot 3395725Sroot default: 3406334Ssam printf("dmc%d: unknown address type %d\n", unit, 3416334Ssam ui->ui_flags & DMC_AF); 3425725Sroot goto setup; 3435725Sroot } 3445725Sroot m = if_rubaget(&sc->sc_ifuba, len, 0); 3455725Sroot if (m == 0) 3465725Sroot goto setup; 3476207Swnj if (IF_QFULL(inq)) { 3486207Swnj IF_DROP(inq); 3499176Ssam m_freem(m); 3506207Swnj } else 3516207Swnj IF_ENQUEUE(inq, m); 3525725Sroot 3535725Sroot setup: 3545725Sroot arg = sc->sc_ifuba.ifu_r.ifrw_info & 0x3ffff; 3555725Sroot dmcload(sc, DMC_READ, arg, ((arg >> 2) & DMC_XMEM) | DMCMTU); 3565725Sroot return; 3575725Sroot 3585725Sroot case DMC_OUX: 3595725Sroot /* 3605725Sroot * A write has completed, start another 3615725Sroot * transfer if there is more data to send. 3625725Sroot */ 3635725Sroot if (sc->sc_oactive == 0) 3645725Sroot return; /* SHOULD IT BE A FATAL ERROR? */ 3655725Sroot printd(" write done\n"); 3665725Sroot sc->sc_if.if_opackets++; 3675725Sroot sc->sc_oactive = 0; 3685725Sroot if (sc->sc_ifuba.ifu_xtofree) { 3699176Ssam m_freem(sc->sc_ifuba.ifu_xtofree); 3705725Sroot sc->sc_ifuba.ifu_xtofree = 0; 3715725Sroot } 3725725Sroot if (sc->sc_if.if_snd.ifq_head == 0) 3735725Sroot return; 3745725Sroot dmcstart(unit); 3755725Sroot return; 3765725Sroot 3775725Sroot case DMC_CNTLO: 3785725Sroot arg &= DMC_CNTMASK; 3795725Sroot if (arg&DMC_FATAL) { 3805725Sroot addr->bsel1 = DMC_MCLR; 3815725Sroot sc->sc_flag &= ~DMCRUN; 3825725Sroot /*** DO SOMETHING TO RESTART DEVICE ***/ 3835725Sroot printf("DMC FATAL ERROR 0%o\n", arg); 3845725Sroot } else { 3855725Sroot /* ACCUMULATE STATISTICS */ 3865725Sroot printf("DMC SOFT ERROR 0%o\n", arg); 3875725Sroot } 3885725Sroot return; 3895725Sroot 3905725Sroot default: 3915725Sroot printf("dmc%d: bad control %o\n", unit, cmd); 3925725Sroot } 3935725Sroot } 3945725Sroot 3955725Sroot /* 3965725Sroot * DMC output routine. 3975725Sroot * Just send the data, header was supplied by 3985725Sroot * upper level protocol routines. 3995725Sroot */ 4006334Ssam dmcoutput(ifp, m, dst) 4015725Sroot register struct ifnet *ifp; 4025725Sroot register struct mbuf *m; 4036334Ssam struct sockaddr *dst; 4045725Sroot { 4055725Sroot struct uba_device *ui = dmcinfo[ifp->if_unit]; 4065725Sroot int s; 4075725Sroot 4085725Sroot printd("dmcoutput\n"); 4096334Ssam if (dst->sa_family != (ui->ui_flags & DMC_AF)) { 4109176Ssam printf("dmc%d: af%d not supported\n", ifp->if_unit, 4119176Ssam dst->sa_family); 4126334Ssam m_freem(m); 4136502Ssam return (EAFNOSUPPORT); 4145725Sroot } 4155725Sroot s = splimp(); 4166207Swnj if (IF_QFULL(&ifp->if_snd)) { 4176207Swnj IF_DROP(&ifp->if_snd); 4186334Ssam m_freem(m); 4196207Swnj splx(s); 4206502Ssam return (ENOBUFS); 4216207Swnj } 4225725Sroot IF_ENQUEUE(&ifp->if_snd, m); 4235725Sroot if (dmc_softc[ifp->if_unit].sc_oactive == 0) 4245725Sroot dmcstart(ifp->if_unit); 4255725Sroot splx(s); 4266502Ssam return (0); 4275725Sroot } 428