1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms are permitted 6 * provided that the above copyright notice and this paragraph are 7 * duplicated in all such forms and that any documentation, 8 * advertising materials, and other materials related to such 9 * distribution and use acknowledge that the software was developed 10 * by the University of California, Berkeley. The name of the 11 * University may not be used to endorse or promote products derived 12 * from this software without specific prior written permission. 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 * @(#)if_cssreg.h 7.2 (Berkeley) 08/04/88 18 */ 19 20 /* 21 * DEC/CSS IMP11-A ARPAnet interface 22 */ 23 24 struct cssdma { 25 short wc; /* word count */ 26 u_short ba; /* bus address (low 16 bits) */ 27 short csr; /* status register */ 28 short db; /* data buffer*/ 29 }; 30 31 struct cssdevice { 32 struct cssdma css_output; /* transmit DR11-B */ 33 struct cssdma css_hole; /* unclever gap */ 34 struct cssdma css_input; /* receive DR11-B */ 35 }; 36 37 #define css_icsr css_input.csr 38 #define css_iba css_input.ba 39 #define css_iwc css_input.wc 40 #define css_ocsr css_output.csr 41 #define css_oba css_output.ba 42 #define css_owc css_output.wc 43 44 /* 45 * Bits Common to both input and out CSR's 46 */ 47 #define CSS_ERR 0x8000 /* error present */ 48 #define CSS_NXM 0x4000 /* non-existant memory */ 49 #define CSS_ATTN 0x2000 /* attention */ 50 #define CSS_MAINT 0x1000 /* maintenance mode */ 51 #define CSS_CYCLE 0x0100 /* force bus cycle */ 52 #define CSS_RDY 0x0080 /* ready */ 53 #define CSS_IE 0x0040 /* interrupt enable */ 54 #define CSS_XA 0x0030 /* extended address bits */ 55 #define CSS_CLR 0x0020 /* clear status (reset) */ 56 #define CSS_GO 0x0001 /* start operation */ 57 58 /* 59 * Input Control Status Register 60 */ 61 #define IN_EOM 0x0800 /* end-of-message recieved */ 62 #define IN_IMPNR 0x0400 /* IMP not ready */ 63 #define IN_RLE 0x0200 /* ready line error */ 64 #define IN_WEN 0x0008 /* write enable */ 65 #define IN_HRDY 0x0004 /* host ready */ 66 67 #define CSS_INBITS \ 68 "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO" 69 70 71 /* 72 * Output Control Status Register 73 */ 74 #define OUT_TXEC 0x0008 /* tx error clear */ 75 #define OUT_ENLB 0x0004 /* enable last bit */ 76 77 #define CSS_OUTBITS \ 78 "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO" 79