123284Smckusick /* 229274Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 335315Sbostic * All rights reserved. 423284Smckusick * 5*44556Sbostic * %sccs.include.redist.c% 635315Sbostic * 7*44556Sbostic * @(#)if_cssreg.h 7.3 (Berkeley) 06/28/90 823284Smckusick */ 97469Ssam 107469Ssam /* 117469Ssam * DEC/CSS IMP11-A ARPAnet interface 127469Ssam */ 137469Ssam 147469Ssam struct cssdma { 157469Ssam short wc; /* word count */ 167469Ssam u_short ba; /* bus address (low 16 bits) */ 177469Ssam short csr; /* status register */ 187469Ssam short db; /* data buffer*/ 197469Ssam }; 207469Ssam 217469Ssam struct cssdevice { 227469Ssam struct cssdma css_output; /* transmit DR11-B */ 237469Ssam struct cssdma css_hole; /* unclever gap */ 247469Ssam struct cssdma css_input; /* receive DR11-B */ 257469Ssam }; 267469Ssam 277469Ssam #define css_icsr css_input.csr 287469Ssam #define css_iba css_input.ba 297469Ssam #define css_iwc css_input.wc 307469Ssam #define css_ocsr css_output.csr 317469Ssam #define css_oba css_output.ba 327469Ssam #define css_owc css_output.wc 337469Ssam 347469Ssam /* 357469Ssam * Bits Common to both input and out CSR's 367469Ssam */ 377469Ssam #define CSS_ERR 0x8000 /* error present */ 387469Ssam #define CSS_NXM 0x4000 /* non-existant memory */ 397469Ssam #define CSS_ATTN 0x2000 /* attention */ 407469Ssam #define CSS_MAINT 0x1000 /* maintenance mode */ 417469Ssam #define CSS_CYCLE 0x0100 /* force bus cycle */ 427469Ssam #define CSS_RDY 0x0080 /* ready */ 437469Ssam #define CSS_IE 0x0040 /* interrupt enable */ 447469Ssam #define CSS_XA 0x0030 /* extended address bits */ 457469Ssam #define CSS_CLR 0x0020 /* clear status (reset) */ 467469Ssam #define CSS_GO 0x0001 /* start operation */ 477469Ssam 487469Ssam /* 497469Ssam * Input Control Status Register 507469Ssam */ 517469Ssam #define IN_EOM 0x0800 /* end-of-message recieved */ 527469Ssam #define IN_IMPNR 0x0400 /* IMP not ready */ 537469Ssam #define IN_RLE 0x0200 /* ready line error */ 547469Ssam #define IN_WEN 0x0008 /* write enable */ 557469Ssam #define IN_HRDY 0x0004 /* host ready */ 567469Ssam 577469Ssam #define CSS_INBITS \ 587469Ssam "\20\20ERR\17NXM\16ATTN\15MAINT\14EOM\13IMPNR\12RLE\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4WE\3HRDY\2CLR\1GO" 597469Ssam 607469Ssam 617469Ssam /* 627469Ssam * Output Control Status Register 637469Ssam */ 647469Ssam #define OUT_TXEC 0x0008 /* tx error clear */ 657469Ssam #define OUT_ENLB 0x0004 /* enable last bit */ 667469Ssam 677469Ssam #define CSS_OUTBITS \ 687469Ssam "\20\20ERR\17NXM\16ATTN\15MAINT\11CYCLE\10RDY\7IE\6XBA17\5XBA16\4TXEC\3ENLB\2CLR\1GO" 69