123283Smckusick /* 223283Smckusick * Copyright (c) 1982 Regents of the University of California. 323283Smckusick * All rights reserved. The Berkeley software License Agreement 423283Smckusick * specifies the terms and conditions for redistribution. 523283Smckusick * 6*24800Skarels * @(#)if_css.c 6.5 (Berkeley) 09/16/85 723283Smckusick */ 87468Ssam 97468Ssam #include "css.h" 107468Ssam 117468Ssam /* 127468Ssam * DEC/CSS IMP11-A ARPAnet IMP interface driver. 137468Ssam * Since "imp11a" is such a mouthful, it is called 147468Ssam * "css" after the LH/DH being called "acc". 157468Ssam * 167468Ssam * Configuration notes: 177468Ssam * 187468Ssam * As delivered from DEC/CSS, it 197468Ssam * is addressed and vectored as two DR11-B's. This makes 207468Ssam * Autoconfig almost IMPOSSIBLE. To make it work, the 217468Ssam * interrupt vectors must be restrapped to make the vectors 227468Ssam * consecutive. The 020 hole between the CSR addresses is 237468Ssam * tolerated, althought that could be cleaned-up also. 247468Ssam * 257468Ssam * Additionally, the TRANSMIT side of the IMP11-A has the 267468Ssam * lower address of the two subunits, so the vector ordering 277468Ssam * in the CONFIG file is reversed from most other devices. 287468Ssam * It should be: 297468Ssam * 307468Ssam * device css0 .... cssxint cssrint 317468Ssam * 327468Ssam * If you get it wrong, it will still autoconfig, but will just 33*24800Skarels * sit there with RECEIVE IDLE indicated on the front panel. 347468Ssam */ 359794Ssam #include "../machine/pte.h" 367468Ssam 3717110Sbloom #include "param.h" 3817110Sbloom #include "systm.h" 3917110Sbloom #include "mbuf.h" 4017110Sbloom #include "buf.h" 4117110Sbloom #include "protosw.h" 4217110Sbloom #include "socket.h" 4317110Sbloom #include "vmmac.h" 448459Sroot 457468Ssam #include "../net/if.h" 468415Swnj #include "../netimp/if_imp.h" 478459Sroot 488459Sroot #include "../vax/cpu.h" 498459Sroot #include "../vax/mtpr.h" 5017110Sbloom #include "if_cssreg.h" 5117110Sbloom #include "if_uba.h" 528459Sroot #include "../vaxuba/ubareg.h" 538459Sroot #include "../vaxuba/ubavar.h" 547468Ssam 557468Ssam int cssprobe(), cssattach(), cssrint(), cssxint(); 567468Ssam struct uba_device *cssinfo[NCSS]; 577468Ssam u_short cssstd[] = { 0 }; 587468Ssam struct uba_driver cssdriver = 597468Ssam { cssprobe, 0, cssattach, 0, cssstd, "css", cssinfo }; 607468Ssam #define CSSUNIT(x) minor(x) 617468Ssam 627468Ssam int cssinit(), cssstart(), cssreset(); 637468Ssam 647468Ssam /* 657468Ssam * "Lower half" of IMP interface driver. 667468Ssam * 677468Ssam * Each IMP interface is handled by a common module which handles 687468Ssam * the IMP-host protocol and a hardware driver which manages the 697468Ssam * hardware specific details of talking with the IMP. 707468Ssam * 717468Ssam * The hardware portion of the IMP driver handles DMA and related 727468Ssam * management of UNIBUS resources. The IMP protocol module interprets 737468Ssam * contents of these messages and "controls" the actions of the 747468Ssam * hardware module during IMP resets, but not, for instance, during 757468Ssam * UNIBUS resets. 767468Ssam * 777468Ssam * The two modules are coupled at "attach time", and ever after, 787468Ssam * through the imp interface structure. Higher level protocols, 797468Ssam * e.g. IP, interact with the IMP driver, rather than the CSS. 807468Ssam */ 817468Ssam struct css_softc { 827468Ssam struct ifnet *css_if; /* pointer to IMP's ifnet struct */ 837468Ssam struct impcb *css_ic; /* data structure shared with IMP */ 847468Ssam struct ifuba css_ifuba; /* UNIBUS resources */ 857468Ssam struct mbuf *css_iq; /* input reassembly queue */ 867468Ssam short css_olen; /* size of last message sent */ 877468Ssam char css_flush; /* flush remainder of message */ 887468Ssam } css_softc[NCSS]; 897468Ssam 907468Ssam /* 917468Ssam * Reset the IMP and cause a transmitter interrupt by 927468Ssam * performing a null DMA. 937468Ssam */ 947468Ssam cssprobe(reg) 957468Ssam caddr_t reg; 967468Ssam { 977468Ssam register int br, cvec; /* r11, r10 value-result */ 987468Ssam register struct cssdevice *addr = (struct cssdevice *)reg; 997468Ssam 1007468Ssam #ifdef lint 1017468Ssam br = 0; cvec = br; br = cvec; 1027468Ssam cssrint(0); cssxint(0); 1037468Ssam #endif 1047468Ssam 1057468Ssam 1067468Ssam addr->css_icsr = CSS_CLR; 1077468Ssam addr->css_ocsr = CSS_CLR; 1087468Ssam DELAY(50000); 1097468Ssam addr->css_icsr = 0; 1107468Ssam addr->css_ocsr = 0; 1117468Ssam DELAY(50000); 1127468Ssam 1137468Ssam addr->css_oba = 0; 1147468Ssam addr->css_owc = -1; 1157468Ssam addr->css_ocsr = CSS_IE | CSS_GO; /* enable interrupts */ 1167468Ssam DELAY(50000); 1177468Ssam addr->css_ocsr = 0; 1187468Ssam 1197468Ssam return (1); 1207468Ssam } 1217468Ssam 1227468Ssam /* 1237468Ssam * Call the IMP module to allow it to set up its internal 1247468Ssam * state, then tie the two modules together by setting up 1257468Ssam * the back pointers to common data structures. 1267468Ssam */ 1277468Ssam cssattach(ui) 1287468Ssam struct uba_device *ui; 1297468Ssam { 1307468Ssam register struct css_softc *sc = &css_softc[ui->ui_unit]; 1317468Ssam register struct impcb *ip; 1327468Ssam struct ifimpcb { 1337468Ssam struct ifnet ifimp_if; 1347468Ssam struct impcb ifimp_impcb; 1357468Ssam } *ifimp; 1367468Ssam 1378831Sroot if ((ifimp = (struct ifimpcb *)impattach(ui, cssreset)) == 0) 138*24800Skarels return; 1397468Ssam sc->css_if = &ifimp->ifimp_if; 1407468Ssam ip = &ifimp->ifimp_impcb; 1417468Ssam sc->css_ic = ip; 1427468Ssam ip->ic_init = cssinit; 1437468Ssam ip->ic_start = cssstart; 1447468Ssam sc->css_ifuba.ifu_flags = UBA_CANTWAIT | UBA_NEED16; 1457468Ssam #ifdef notdef 1467468Ssam sc->css_ifuba.ifu_flags =| UBA_NEEDBDP; 1477468Ssam #endif 1487468Ssam } 1497468Ssam 1507468Ssam /* 1517468Ssam * Reset interface after UNIBUS reset. 1527468Ssam * If interface is on specified uba, reset its state. 1537468Ssam */ 1547468Ssam cssreset(unit, uban) 1557468Ssam int unit, uban; 1567468Ssam { 1577468Ssam register struct uba_device *ui; 1587468Ssam struct css_softc *sc; 1597468Ssam 1607468Ssam if (unit >= NCSS || (ui = cssinfo[unit]) == 0 || ui->ui_alive == 0 || 1617468Ssam ui->ui_ubanum != uban) 1627468Ssam return; 1637468Ssam printf(" css%d", unit); 1647468Ssam sc = &css_softc[unit]; 16521778Skarels sc->css_if->if_flags &= ~IFF_RUNNING; 1667468Ssam /* must go through IMP to allow it to set state */ 1677468Ssam (*sc->css_if->if_init)(unit); 1687468Ssam } 1697468Ssam 1707468Ssam /* 1717468Ssam * Initialize interface: clear recorded pending operations, 1727468Ssam * and retrieve, and reinitialize UNIBUS resources. 1737468Ssam */ 1747468Ssam cssinit(unit) 1757468Ssam int unit; 1767468Ssam { 1777468Ssam register struct css_softc *sc; 1787468Ssam register struct uba_device *ui; 1797468Ssam register struct cssdevice *addr; 1807468Ssam int x, info; 1817468Ssam 1827468Ssam if (unit >= NCSS || (ui = cssinfo[unit]) == 0 || ui->ui_alive == 0) { 1837468Ssam printf("css%d: not alive\n", unit); 1847468Ssam return(0); 1857468Ssam } 1867468Ssam sc = &css_softc[unit]; 1877468Ssam 1887468Ssam /* 1897468Ssam * Header length is 0 to if_ubainit since we have to pass 1907468Ssam * the IMP leader up to the protocol interpretaion 1917468Ssam * routines. If we had the deader length as 1927468Ssam * sizeof(struct imp_leader), then the if_ routines 1937468Ssam * would assume we handle it on input and output. 1947468Ssam */ 1957468Ssam 1967468Ssam if (if_ubainit(&sc->css_ifuba, ui->ui_ubanum, 0,(int)btoc(IMPMTU)) == 0) { 1977468Ssam printf("css%d: can't initialize\n", unit); 1987468Ssam ui->ui_alive = 0; 199*24800Skarels sc->css_if->if_flags &= ~(IFF_UP | IFF_RUNNING); 2007468Ssam return(0); 2017468Ssam } 20221778Skarels sc->css_if->if_flags |= IFF_RUNNING; 2037468Ssam addr = (struct cssdevice *)ui->ui_addr; 2047468Ssam 2057468Ssam /* reset the imp interface. */ 2067468Ssam x = spl5(); 2077468Ssam addr->css_icsr = CSS_CLR; 2087468Ssam addr->css_ocsr = CSS_CLR; 2097468Ssam DELAY(100); 2107468Ssam addr->css_icsr = 0; 2117468Ssam addr->css_ocsr = 0; 2127468Ssam addr->css_icsr = IN_HRDY; /* close the relay */ 2137468Ssam DELAY(5000); 2147468Ssam splx(x); 2157468Ssam 2167468Ssam /* 2177468Ssam * This may hang if the imp isn't really there. 2187468Ssam * Will test and verify safe operation. 2197468Ssam */ 2207468Ssam 2217468Ssam x = 500; 2227468Ssam while (x-- > 0) { 2237468Ssam if ((addr->css_icsr & (IN_HRDY|IN_IMPNR)) == IN_HRDY) 2247468Ssam break; 2257468Ssam addr->css_icsr = IN_HRDY; /* close the relay */ 2267468Ssam DELAY(5000); 2277468Ssam } 2287468Ssam 2297468Ssam if (x <= 0) { 2307468Ssam printf("css%d: imp doesn't respond, icsr=%b\n", unit, 2317468Ssam CSS_INBITS, addr->css_icsr); 2327468Ssam goto down; 2337468Ssam } 2347468Ssam 2357468Ssam /* 2367468Ssam * Put up a read. We can't restart any outstanding writes 2377468Ssam * until we're back in synch with the IMP (i.e. we've flushed 2387468Ssam * the NOOPs it throws at us). 2397468Ssam * Note: IMPMTU includes the leader. 2407468Ssam */ 2417468Ssam 2427468Ssam x = spl5(); 2437468Ssam info = sc->css_ifuba.ifu_r.ifrw_info; 2447468Ssam addr->css_iba = (u_short)info; 2457468Ssam addr->css_iwc = -(IMPMTU >> 1); 2467468Ssam addr->css_icsr = 2477468Ssam IN_HRDY | CSS_IE | IN_WEN | ((info & 0x30000) >> 12) | CSS_GO; 2487468Ssam splx(x); 2497468Ssam return(1); 2507468Ssam 2517468Ssam down: 2527468Ssam ui->ui_alive = 0; 2537468Ssam return(0); 2547468Ssam } 2557468Ssam 2567468Ssam /* 2577468Ssam * Start output on an interface. 2587468Ssam */ 2597468Ssam cssstart(dev) 2607468Ssam dev_t dev; 2617468Ssam { 2627468Ssam int unit = CSSUNIT(dev), info; 2637468Ssam struct uba_device *ui = cssinfo[unit]; 2647468Ssam register struct css_softc *sc = &css_softc[unit]; 2657468Ssam register struct cssdevice *addr; 2667468Ssam struct mbuf *m; 2677468Ssam u_short cmd; 2687468Ssam 2697468Ssam if (sc->css_ic->ic_oactive) 2707468Ssam goto restart; 2717468Ssam 2727468Ssam /* 2737468Ssam * Not already active, deqeue a request and 2747468Ssam * map it onto the UNIBUS. If no more 2757468Ssam * requeusts, just return. 2767468Ssam */ 2777468Ssam IF_DEQUEUE(&sc->css_if->if_snd, m); 2787468Ssam if (m == 0) { 2797468Ssam sc->css_ic->ic_oactive = 0; 2807468Ssam return; 2817468Ssam } 2827468Ssam sc->css_olen = if_wubaput(&sc->css_ifuba, m); 2837468Ssam 2847468Ssam restart: 2857468Ssam /* 2867468Ssam * Have request mapped to UNIBUS for transmission. 2877468Ssam * Purge any stale data from the BDP, and start the output. 2887468Ssam */ 2897468Ssam if (sc->css_ifuba.ifu_flags & UBA_NEEDBDP) 2907468Ssam UBAPURGE(sc->css_ifuba.ifu_uba, sc->css_ifuba.ifu_w.ifrw_bdp); 2917468Ssam addr = (struct cssdevice *)ui->ui_addr; 2927468Ssam info = sc->css_ifuba.ifu_w.ifrw_info; 2937468Ssam addr->css_oba = (u_short)info; 2947468Ssam addr->css_owc = -((sc->css_olen + 1) >> 1); 2957468Ssam cmd = CSS_IE | OUT_ENLB | ((info & 0x30000) >> 12) | CSS_GO; 2967468Ssam addr->css_ocsr = cmd; 2977468Ssam sc->css_ic->ic_oactive = 1; 2987468Ssam } 2997468Ssam 3007468Ssam /* 3017468Ssam * Output interrupt handler. 3027468Ssam */ 3037468Ssam cssxint(unit) 3047468Ssam { 3057468Ssam register struct uba_device *ui = cssinfo[unit]; 3067468Ssam register struct css_softc *sc = &css_softc[unit]; 3077468Ssam register struct cssdevice *addr; 3087468Ssam 3097468Ssam addr = (struct cssdevice *)ui->ui_addr; 3107468Ssam if (sc->css_ic->ic_oactive == 0) { 3117468Ssam printf("css%d: stray output interrupt csr=%b\n", 3127468Ssam unit, addr->css_ocsr, CSS_OUTBITS); 3137468Ssam return; 3147468Ssam } 3157468Ssam sc->css_if->if_opackets++; 3167468Ssam sc->css_ic->ic_oactive = 0; 3177468Ssam if (addr->css_ocsr & CSS_ERR){ 3187468Ssam sc->css_if->if_oerrors++; 3197468Ssam printf("css%d: output error, ocsr=%b icsr=%b\n", unit, 3207468Ssam addr->css_ocsr, CSS_OUTBITS, 3217468Ssam addr->css_icsr, CSS_INBITS); 3227468Ssam } 3237468Ssam if (sc->css_ifuba.ifu_xtofree) { 3247468Ssam m_freem(sc->css_ifuba.ifu_xtofree); 3257468Ssam sc->css_ifuba.ifu_xtofree = 0; 3267468Ssam } 3277468Ssam if (sc->css_if->if_snd.ifq_head) 3287468Ssam cssstart(unit); 3297468Ssam } 3307468Ssam 3317468Ssam /* 3327468Ssam * Input interrupt handler 3337468Ssam */ 3347468Ssam cssrint(unit) 3357468Ssam { 3367468Ssam register struct css_softc *sc = &css_softc[unit]; 3377468Ssam register struct cssdevice *addr; 3387468Ssam struct mbuf *m; 3397468Ssam int len, info; 3407468Ssam 3417468Ssam sc->css_if->if_ipackets++; 3427468Ssam 3437468Ssam /* 3447468Ssam * Purge BDP; flush message if error indicated. 3457468Ssam */ 3467468Ssam 3477468Ssam addr = (struct cssdevice *)cssinfo[unit]->ui_addr; 3487468Ssam if (sc->css_ifuba.ifu_flags & UBA_NEEDBDP) 3497468Ssam UBAPURGE(sc->css_ifuba.ifu_uba, sc->css_ifuba.ifu_r.ifrw_bdp); 3507468Ssam if (addr->css_icsr & CSS_ERR) { 3517468Ssam printf("css%d: recv error, csr=%b\n", unit, 3527468Ssam addr->css_icsr, CSS_INBITS); 3537468Ssam sc->css_if->if_ierrors++; 3547468Ssam sc->css_flush = 1; 3557468Ssam } 3567468Ssam 3577468Ssam if (sc->css_flush) { 3587468Ssam if (addr->css_icsr & IN_EOM) 3597468Ssam sc->css_flush = 0; 3607468Ssam goto setup; 3617468Ssam } 3627468Ssam 3637468Ssam len = IMPMTU + (addr->css_iwc << 1); 3647468Ssam if (len < 0 || len > IMPMTU) { 3657468Ssam printf("css%d: bad length=%d\n", len); 3667468Ssam sc->css_if->if_ierrors++; 3677468Ssam goto setup; 3687468Ssam } 3697468Ssam 3707468Ssam /* 371*24800Skarels * The offset parameter is always 0 since using 3727468Ssam * trailers on the ARPAnet is insane. 3737468Ssam */ 374*24800Skarels m = if_rubaget(&sc->css_ifuba, len, 0, &sc->css_if); 3757468Ssam if (m == 0) 3767468Ssam goto setup; 3777468Ssam if ((addr->css_icsr & IN_EOM) == 0) { 3787468Ssam if (sc->css_iq) 3797468Ssam m_cat(sc->css_iq, m); 3807468Ssam else 3817468Ssam sc->css_iq = m; 3827468Ssam goto setup; 3837468Ssam } 3847468Ssam if (sc->css_iq) { 3857468Ssam m_cat(sc->css_iq, m); 3867468Ssam m = sc->css_iq; 3877468Ssam sc->css_iq = 0; 3887468Ssam } 3897468Ssam impinput(unit, m); 3907468Ssam 3917468Ssam setup: 3927468Ssam /* 3937468Ssam * Setup for next message. 3947468Ssam */ 3957468Ssam info = sc->css_ifuba.ifu_r.ifrw_info; 3967468Ssam addr->css_iba = (u_short)info; 3977468Ssam addr->css_iwc = - (IMPMTU >> 1); 3987468Ssam addr->css_icsr = 3997468Ssam IN_HRDY | CSS_IE | IN_WEN | ((info & 0x30000) >> 12) | CSS_GO; 4007468Ssam } 401