123282Smckusick /* 229273Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 3*35314Sbostic * All rights reserved. 423282Smckusick * 5*35314Sbostic * Redistribution and use in source and binary forms are permitted 6*35314Sbostic * provided that the above copyright notice and this paragraph are 7*35314Sbostic * duplicated in all such forms and that any documentation, 8*35314Sbostic * advertising materials, and other materials related to such 9*35314Sbostic * distribution and use acknowledge that the software was developed 10*35314Sbostic * by the University of California, Berkeley. The name of the 11*35314Sbostic * University may not be used to endorse or promote products derived 12*35314Sbostic * from this software without specific prior written permission. 13*35314Sbostic * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14*35314Sbostic * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15*35314Sbostic * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16*35314Sbostic * 17*35314Sbostic * @(#)if_accreg.h 7.2 (Berkeley) 08/04/88 1823282Smckusick */ 195699Sroot 205699Sroot /* 215699Sroot * ACC LH/DH-11 interface 225699Sroot */ 235699Sroot 245699Sroot struct accdma { 255699Sroot short csr; /* control and status */ 265699Sroot short db; /* data buffer */ 275699Sroot u_short ba; /* buss address */ 285699Sroot short wc; /* word count */ 295699Sroot }; 305699Sroot 315699Sroot struct accdevice { 325699Sroot struct accdma input; 335699Sroot struct accdma output; 345699Sroot }; 355699Sroot 365699Sroot #define icsr input.csr 375699Sroot #define iba input.ba 385699Sroot #define iwc input.wc 395699Sroot #define ocsr output.csr 405699Sroot #define oba output.ba 415699Sroot #define owc output.wc 425699Sroot 435699Sroot /* 445699Sroot * Bits Common to both input and out CSR's 455699Sroot */ 465699Sroot #define ACC_ERR 0x8000 /* error present */ 475699Sroot #define ACC_NXM 0x4000 /* non-existant memory */ 485699Sroot #define ACC_RDY 0x0080 /* ready */ 495921Ssam #define ACC_IE 0x0040 /* interrupt enable */ 505699Sroot #define ACC_RESET 0x0002 /* reset interface */ 515699Sroot #define ACC_GO 0x0001 /* start operation */ 525699Sroot 535699Sroot /* 545699Sroot * Input Control Status Register 555699Sroot */ 565699Sroot #define IN_EOM 0x2000 /* end-of-message recieved */ 575699Sroot #define IN_HRDY 0x0800 /* host ready */ 585699Sroot #define IN_IMPBSY 0x0400 /* IMP not ready */ 595699Sroot #define IN_RMR 0x0200 /* receive master ready error */ 605699Sroot #define IN_IBF 0x0100 /* input data buffer full */ 615699Sroot #define IN_WEN 0x0008 /* write enable */ 625699Sroot #define IN_MRDY 0x0004 /* master ready */ 635699Sroot 645699Sroot #define ACC_INBITS \ 655699Sroot "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 665699Sroot \4WEN\3MRDY\2RESET\1GO" 675699Sroot 685699Sroot /* 695699Sroot * Output Control Status Register 705699Sroot */ 715699Sroot #define OUT_TMR 0x0200 /* transmit master ready error */ 725699Sroot #define OUT_BBACK 0x0008 /* bus back */ 735699Sroot #define OUT_ENLB 0x0004 /* enable last bit */ 745699Sroot 755699Sroot #define ACC_OUTBITS \ 765699Sroot "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 77