1*23282Smckusick /* 2*23282Smckusick * Copyright (c) 1982 Regents of the University of California. 3*23282Smckusick * All rights reserved. The Berkeley software License Agreement 4*23282Smckusick * specifies the terms and conditions for redistribution. 5*23282Smckusick * 6*23282Smckusick * @(#)if_accreg.h 6.2 (Berkeley) 06/08/85 7*23282Smckusick */ 85699Sroot 95699Sroot /* 105699Sroot * ACC LH/DH-11 interface 115699Sroot */ 125699Sroot 135699Sroot struct accdma { 145699Sroot short csr; /* control and status */ 155699Sroot short db; /* data buffer */ 165699Sroot u_short ba; /* buss address */ 175699Sroot short wc; /* word count */ 185699Sroot }; 195699Sroot 205699Sroot struct accdevice { 215699Sroot struct accdma input; 225699Sroot struct accdma output; 235699Sroot }; 245699Sroot 255699Sroot #define icsr input.csr 265699Sroot #define iba input.ba 275699Sroot #define iwc input.wc 285699Sroot #define ocsr output.csr 295699Sroot #define oba output.ba 305699Sroot #define owc output.wc 315699Sroot 325699Sroot /* 335699Sroot * Bits Common to both input and out CSR's 345699Sroot */ 355699Sroot #define ACC_ERR 0x8000 /* error present */ 365699Sroot #define ACC_NXM 0x4000 /* non-existant memory */ 375699Sroot #define ACC_RDY 0x0080 /* ready */ 385921Ssam #define ACC_IE 0x0040 /* interrupt enable */ 395699Sroot #define ACC_RESET 0x0002 /* reset interface */ 405699Sroot #define ACC_GO 0x0001 /* start operation */ 415699Sroot 425699Sroot /* 435699Sroot * Input Control Status Register 445699Sroot */ 455699Sroot #define IN_EOM 0x2000 /* end-of-message recieved */ 465699Sroot #define IN_HRDY 0x0800 /* host ready */ 475699Sroot #define IN_IMPBSY 0x0400 /* IMP not ready */ 485699Sroot #define IN_RMR 0x0200 /* receive master ready error */ 495699Sroot #define IN_IBF 0x0100 /* input data buffer full */ 505699Sroot #define IN_WEN 0x0008 /* write enable */ 515699Sroot #define IN_MRDY 0x0004 /* master ready */ 525699Sroot 535699Sroot #define ACC_INBITS \ 545699Sroot "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 555699Sroot \4WEN\3MRDY\2RESET\1GO" 565699Sroot 575699Sroot /* 585699Sroot * Output Control Status Register 595699Sroot */ 605699Sroot #define OUT_TMR 0x0200 /* transmit master ready error */ 615699Sroot #define OUT_BBACK 0x0008 /* bus back */ 625699Sroot #define OUT_ENLB 0x0004 /* enable last bit */ 635699Sroot 645699Sroot #define ACC_OUTBITS \ 655699Sroot "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 66