123282Smckusick /* 229273Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 335314Sbostic * All rights reserved. 423282Smckusick * 5*44556Sbostic * %sccs.include.redist.c% 635314Sbostic * 7*44556Sbostic * @(#)if_accreg.h 7.3 (Berkeley) 06/28/90 823282Smckusick */ 95699Sroot 105699Sroot /* 115699Sroot * ACC LH/DH-11 interface 125699Sroot */ 135699Sroot 145699Sroot struct accdma { 155699Sroot short csr; /* control and status */ 165699Sroot short db; /* data buffer */ 175699Sroot u_short ba; /* buss address */ 185699Sroot short wc; /* word count */ 195699Sroot }; 205699Sroot 215699Sroot struct accdevice { 225699Sroot struct accdma input; 235699Sroot struct accdma output; 245699Sroot }; 255699Sroot 265699Sroot #define icsr input.csr 275699Sroot #define iba input.ba 285699Sroot #define iwc input.wc 295699Sroot #define ocsr output.csr 305699Sroot #define oba output.ba 315699Sroot #define owc output.wc 325699Sroot 335699Sroot /* 345699Sroot * Bits Common to both input and out CSR's 355699Sroot */ 365699Sroot #define ACC_ERR 0x8000 /* error present */ 375699Sroot #define ACC_NXM 0x4000 /* non-existant memory */ 385699Sroot #define ACC_RDY 0x0080 /* ready */ 395921Ssam #define ACC_IE 0x0040 /* interrupt enable */ 405699Sroot #define ACC_RESET 0x0002 /* reset interface */ 415699Sroot #define ACC_GO 0x0001 /* start operation */ 425699Sroot 435699Sroot /* 445699Sroot * Input Control Status Register 455699Sroot */ 465699Sroot #define IN_EOM 0x2000 /* end-of-message recieved */ 475699Sroot #define IN_HRDY 0x0800 /* host ready */ 485699Sroot #define IN_IMPBSY 0x0400 /* IMP not ready */ 495699Sroot #define IN_RMR 0x0200 /* receive master ready error */ 505699Sroot #define IN_IBF 0x0100 /* input data buffer full */ 515699Sroot #define IN_WEN 0x0008 /* write enable */ 525699Sroot #define IN_MRDY 0x0004 /* master ready */ 535699Sroot 545699Sroot #define ACC_INBITS \ 555699Sroot "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 565699Sroot \4WEN\3MRDY\2RESET\1GO" 575699Sroot 585699Sroot /* 595699Sroot * Output Control Status Register 605699Sroot */ 615699Sroot #define OUT_TMR 0x0200 /* transmit master ready error */ 625699Sroot #define OUT_BBACK 0x0008 /* bus back */ 635699Sroot #define OUT_ENLB 0x0004 /* enable last bit */ 645699Sroot 655699Sroot #define ACC_OUTBITS \ 665699Sroot "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 67