134293Skarels /* 235041Sbostic * Copyright (c) 1988 Regents of the University of California. 335041Sbostic * All rights reserved. 435041Sbostic * 535041Sbostic * This code is derived from software contributed to Berkeley by 635041Sbostic * Chris Torek. 735041Sbostic * 8*44542Sbostic * %sccs.include.redist.c% 935041Sbostic * 10*44542Sbostic * @(#)nireg.h 7.3 (Berkeley) 06/28/90 1135041Sbostic */ 1235041Sbostic 1335041Sbostic /* 1434293Skarels * Registers for the DEBNA and DEBNK Ethernet interfaces 1534293Skarels * (DEC calls these Network Interfaces, hence nireg.h) 1634293Skarels */ 1734293Skarels 1834293Skarels /* 1934293Skarels * this seems to be intended to be more general, but I have no details, 2034293Skarels * so it goes here for now 2134293Skarels * 2234293Skarels * BI Vax Port (BVP) stuff first: 2334293Skarels */ 2434293Skarels struct bvpregs { 2534293Skarels u_long p_pcr; /* port control register */ 2634293Skarels u_long p_psr; /* port status register */ 2734293Skarels u_long p_per; /* port error register */ 2834293Skarels u_long p_pdr; /* port data register */ 2934293Skarels }; 3034293Skarels 3134293Skarels /* 3234293Skarels * BI node space registers 3334293Skarels */ 3434293Skarels struct ni_regs { 3534293Skarels struct biiregs ni_bi; /* BIIC registers, except GPRs */ 3634293Skarels struct bvpregs ni_tkp; /* tk50 port control via BIIC GPRs */ 3734293Skarels u_long ni_xxx[64]; /* unused */ 3834293Skarels u_long ni_rxcd; /* receive console data */ 3934293Skarels struct bvpregs ni_nip; /* NI port control via BCI3 GPRs */ 4034293Skarels u_long ni_pudr; /* power-up diagnostic register */ 4134293Skarels }; 4234293Skarels 4334293Skarels /* bits in ni_pudr */ 4434293Skarels #define PUDR_TAPE 0x40000000 /* tk50 & assoc logic ok */ 4534293Skarels #define PUDR_PATCH 0x20000000 /* patch logic ok */ 4634293Skarels #define PUDR_VRAM 0x10000000 /* DEBNx onboard RAM ok */ 4734293Skarels #define PUDR_VROM1 0x08000000 /* uVax ROM 1 ok */ /* ? */ 4834293Skarels #define PUDR_VROM2 0x04000000 /* uVax ROM 2 ok */ 4934293Skarels #define PUDR_VROM3 0x02000000 /* uVax ROM 3 ok */ 5034293Skarels #define PUDR_VROM4 0x01000000 /* uVax ROM 4 ok */ 5134293Skarels #define PUDR_UVAX 0x00800000 /* uVax passes self test */ 5234293Skarels #define PUDR_BI 0x00400000 /* BIIC and BCI3 chips ok */ 5334293Skarels #define PUDR_TMR 0x00200000 /* interval timer ok */ 5434293Skarels #define PUDR_IRQ 0x00100000 /* no IRQ lines stuck */ 5534293Skarels #define PUDR_NI 0x00080000 /* Ethernet ctlr ok */ 5634293Skarels #define PUDR_TK50 0x00040000 /* tk50 present */ 5734293Skarels #define PUDR_PRES 0x00001000 /* tk50 present (again?!) */ 5834293Skarels #define PUDR_UVINT 0x00000800 /* uVax-to-80186 intr logic ok */ 5934293Skarels #define PUDR_BUSHD 0x00000400 /* no bus hold errors */ 6034293Skarels #define PUDR_II32 0x00000200 /* II32 transceivers ok */ 6134293Skarels #define PUDR_MPSC 0x00000100 /* MPSC logic ok */ 6234293Skarels #define PUDR_GAP 0x00000080 /* gap-detect logic ok */ 6334293Skarels #define PUDR_MISC 0x00000040 /* misc. registers ok */ 6434293Skarels #define PUDR_UNEXP 0x00000020 /* unexpected interrupt trapped */ 6534293Skarels #define PUDR_80186 0x00000010 /* 80186 ok */ 6634293Skarels #define PUDR_PATCH 0x00000008 /* patch logic ok (again) */ 6734293Skarels #define PUDR_8RAM 0x00000004 /* 80186 RAM ok */ 6834293Skarels #define PUDR_8ROM2 0x00000002 /* 80186 ROM1 ok */ 6934293Skarels #define PUDR_8ROM1 0x00000001 /* 80186 ROM2 ok */ 70