1 /* 2 * Copyright (c) 1986 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms are permitted 6 * provided that the above copyright notice and this paragraph are 7 * duplicated in all such forms and that any documentation, 8 * advertising materials, and other materials related to such 9 * distribution and use acknowledge that the software was developed 10 * by the University of California, Berkeley. The name of the 11 * University may not be used to endorse or promote products derived 12 * from this software without specific prior written permission. 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * 17 * @(#)ikreg.h 7.2 (Berkeley) 09/16/88 18 */ 19 20 /* 21 * IKON DR-11W register definitions. 22 */ 23 struct ikdevice { 24 u_short ik_csr; /* control status register */ 25 u_short ik_data; /* data in/out register */ 26 u_char ik_mod; /* address modifier */ 27 u_char ik_vec; /* interrupt vector */ 28 u_short ik_pulse; /* pulse commands (w) */ 29 u_short ik_fill[5]; 30 u_short ik_balo; /* low word of dma beginning address (w) */ 31 u_short ik_wc; /* dma word count */ 32 u_short ik_calo; /* low word of dma current address (r) */ 33 u_short ik_fill1; 34 u_short ik_bahi; /* high word of dma beginning address (w) */ 35 u_short ik_fill2; 36 u_short ik_cahi; /* high word of dma current address (r) */ 37 }; 38 39 /* 40 * CSR control definitions (write-only). 41 */ 42 #define IKCSR_GO 0x0001 /* start dma */ 43 #define IKCSR_FNC1 0x0002 /* function bit 1 */ 44 #define IKCSR_FNC2 0x0004 /* function bit 2 */ 45 #define IKCSR_FNC3 0x0008 /* function bit 3 */ 46 /* bits 4-5 are unused */ 47 #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ 48 /* bit 7 is unused */ 49 #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ 50 /* bits 9-11 are unused */ 51 #define IKCSR_MCLR 0x1000 /* master clear board */ 52 #define IKCSR_RPERR 0x2000 /* reset parity error */ 53 #define IKCSR_RATTF 0x4000 /* reset attention */ 54 #define IKCSR_RDMAF 0x8000 /* reset dma completion */ 55 56 /* 57 * CSR status definitions (read-only). 58 */ 59 #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ 60 /* bits 1-3 reflect the function latch state */ 61 #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ 62 #define IKCSR_BERR 0x0020 /* bus error during dma */ 63 /* bit 6 reflects interrupt enable state */ 64 #define IKCSR_READY 0x0080 /* device ready for next command */ 65 /* bit 8 should be 0 */ 66 #define IKCSR_STATC 0x0200 /* status bit C */ 67 #define IKCSR_STATB 0x0400 /* status bit B */ 68 #define IKCSR_STATA 0x0800 /* status bit A */ 69 #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ 70 #define IKCSR_ATTN 0x2000 /* current state of attention bit */ 71 #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ 72 #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ 73 74 #define IKCSR_BITS \ 75 "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ 76 \15PERR\16ATTN\17ATTF\20DMAF" 77 78 /* 79 * Pulse command register definitions (write-only). 80 */ 81 #define IKPULSE_GO 0x0001 /* enable dma */ 82 #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ 83 #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ 84 #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ 85 #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ 86 #define IKPULSE_MCLR 0x1000 /* initialize interface */ 87 #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ 88 #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ 89 #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ 90