1*23998Ssam /* udc.h 1.1 85/07/21 */ 2*23998Ssam 3*23998Ssam struct UDPAC { /* UDC command packet */ 4*23998Ssam char _stx ; 5*23998Ssam char _pkid ; 6*23998Ssam char _pksiz ; /* 21 bytes */ 7*23998Ssam char _pkdev ; /* device # */ 8*23998Ssam char _pkcmd ; /* Command type */ 9*23998Ssam char _pkfnc ; /* Function type */ 10*23998Ssam short _pkcnt ; /* # of data blocks (1/4K each) */ 11*23998Ssam short _pbsiz ; /* Block length size (0x100 = 1/4K) */ 12*23998Ssam short _pkmem[2] ; /* Starting memory address.Should be 'long' but 13*23998Ssam we can't write it this way on Tahoe, 14*23998Ssam because of alignment problems - the C 15*23998Ssam will gap after the previous 'short' */ 16*23998Ssam short _pcksm ; /* Checksum (unused) */ 17*23998Ssam long _psecno ; /* Starting sector # */ 18*23998Ssam char _etx ; 19*23998Ssam } 20*23998Ssam ; 21*23998Ssam 22*23998Ssam #define SECTSIZ 256 /* sector size */ 23*23998Ssam #define L2SIZ 8 /* log2 of sector size */ 24*23998Ssam #define L2BSIZ 10 /* log2 of block size */ 25*23998Ssam #define NUDC 1 /* number of UDC controllers */ 26*23998Ssam #define NUNIT 8 /* number of units per controller */ 27*23998Ssam #define NUDDRV 5 /* number of drive types supported */ 28*23998Ssam #define DK_N 1 /* Monitoring device bit */ 29*23998Ssam 30*23998Ssam /* 31*23998Ssam ** Block devices sizes structure 32*23998Ssam */ 33*23998Ssam 34*23998Ssam struct size 35*23998Ssam { 36*23998Ssam daddr_t nblocks; 37*23998Ssam int block0; 38*23998Ssam }; 39*23998Ssam 40*23998Ssam #define udaddr ( (char *)(0xff0000+IOBASE) ) 41*23998Ssam #define INT 0x00d /* interrupt offset */ 42*23998Ssam #define RST 0x00f /* controller reset offset */ 43*23998Ssam #define OB1 0x101 44*23998Ssam #define OB2 0x103 45*23998Ssam #define IB1 0x181 46*23998Ssam #define IB2 0x183 47*23998Ssam #define PKID 0x187 /* packet id */ 48*23998Ssam #define PKLEN 0x189 /* packet length */ 49*23998Ssam #define PKDEV 0x18b /* device # */ 50*23998Ssam #define PKCMD 0x18d /* command type */ 51*23998Ssam #define PKSTT 0x18f /* status type */ 52*23998Ssam #define STAT1 0x191 /* i/o status result offset */ 53*23998Ssam #define STAT2 0x193 54*23998Ssam #define DEVSTAT1 0x195 55*23998Ssam #define DEVSTAT2 0x197 56*23998Ssam #define DEVSIZE 0x199 /* # of sectors in device status message */ 57*23998Ssam 58*23998Ssam #define UDREAD 0x10 59*23998Ssam #define UDWTRY 0x01 /* read with retry */ 60*23998Ssam 61*23998Ssam #define UDWRITE 0x20 62*23998Ssam #define UDWCRC 0x01 /* write sectors and check CRC */ 63*23998Ssam #define UDWSECT 0x02 /* write sectors */ 64*23998Ssam 65*23998Ssam #define UDTEST 0x30 66*23998Ssam #define UDSTAT 0x02 /* Test status */ 67*23998Ssam 68*23998Ssam #define DEVRDY 0x80 /* device ready bit in status byte */ 69*23998Ssam #define DEVTYPE 0x7 /* bits 0-2 in status byte define device */ 70*23998Ssam #define FLP 0x1 71*23998Ssam #define HARDDISK 0x2 72*23998Ssam #define TAPE 0x5 73*23998Ssam 74*23998Ssam /* Some I/O addresses used to generate pulses for scopes */ 75*23998Ssam #define OUT1 0xffffb034 76*23998Ssam #define OUT2 0xffffb018 77*23998Ssam #define OUT3 0xffffb020 78*23998Ssam #define OUT4 0xffffb004 79*23998Ssam #define OUT5 0xffffb024 80*23998Ssam #define OUT6 0xffffb00c 81*23998Ssam #define OUT7 0xffffb02c 82*23998Ssam 83*23998Ssam #define IN1 0xffffb030 84*23998Ssam #define IN2 0xffffb03c 85*23998Ssam #define IN3 0xffffb004 86*23998Ssam #define IN4 0xffffb00c 87*23998Ssam #define IN5 0xffffb02c 88*23998Ssam 89*23998Ssam int dummy; 90*23998Ssam extern char vmem[][16*NBPG]; 91*23998Ssam 92*23998Ssam #define IOaddr(off) (char *)((int)vmem + ((off) & 0x0fffff)) 93*23998Ssam 94*23998Ssam int iospace_mapped; 95*23998Ssam #define scope_out(x) if(iospace_mapped) movob (0, IOaddr(OUT/**/x)) 96*23998Ssam #define scope_in(x) if(iospace_mapped) dummy = *IOaddr(IN/**/x) 97