1*25682Ssam /* mtpr.h 1.1 86/01/05 */ 2*25682Ssam /* mtpr.h 4.5 82/11/05 */ 3*25682Ssam 4*25682Ssam /* 5*25682Ssam * TAHOE processor register numbers 6*25682Ssam */ 7*25682Ssam 8*25682Ssam #define SBR 0x0 /* system base register */ 9*25682Ssam #define SLR 0x1 /* system length register */ 10*25682Ssam #define P0BR 0x2 /* p0 base register */ 11*25682Ssam #define P0LR 0x3 /* p0 length register */ 12*25682Ssam #define P1BR 0x4 /* p1 base register */ 13*25682Ssam #define P1LR 0x5 /* p1 length register */ 14*25682Ssam #define P2BR 0x6 /* p2 base register */ 15*25682Ssam #define P2LR 0x7 /* p2 length register */ 16*25682Ssam #define IPL 0x8 /* interrupt priority level */ 17*25682Ssam #define MME 0x9 /* memory management enable */ 18*25682Ssam #define TBIA 0xa /* translation buffer invalidate all */ 19*25682Ssam #define TBIS 0xb /* translation buffer invalidate single */ 20*25682Ssam #define DCK 0xc /* data cache key */ 21*25682Ssam #define CCK 0xd /* code cache key */ 22*25682Ssam #define PCBB 0xe /* process control block base */ 23*25682Ssam #define ISP 0xf /* interrupt stack pointer */ 24*25682Ssam #define SIRR 0x10 /* software interrupt request */ 25*25682Ssam #define SISR 0x11 /* software interrupt summary */ 26*25682Ssam #define SCBB 0x12 /* system control block base */ 27*25682Ssam #define KSP 0x13 /* kernelack pointer */ 28*25682Ssam #define USP 0x14 /* user stack pointer */ 29*25682Ssam #define CPMDCB 0x15 /* CP master DCM pointer */ 30*25682Ssam #define PACC 0x17 /* purge all code cache */ 31*25682Ssam #define P1DC 0x18 /* purge one data cache */ 32*25682Ssam #define PADC 0x19 /* purge all data cache */ 33*25682Ssam #define HISR 0x1a /* hardware interrupt summery register */ 34*25682Ssam #define DCR 0x1b /* diagnostic control register */ 35*25682Ssam #define PDCS 0x1c /* purge data cache slot */ 36