149429Sbostic /*- 249429Sbostic * Copyright (c) 1986 The Regents of the University of California. 349429Sbostic * All rights reserved. 449429Sbostic * 549429Sbostic * This code is derived from software contributed to Berkeley by 649429Sbostic * Computer Consoles Inc. 749429Sbostic * 849429Sbostic * %sccs.include.proprietary.c% 949429Sbostic * 10*52626Ssklower * @(#)mtpr.h 7.3 (Berkeley) 02/20/92 1134408Skarels */ 1225682Ssam 13*52626Ssklower #ifndef _MTPR_H__ 14*52626Ssklower #define _MTPR_H_ 1525682Ssam /* 1625682Ssam * TAHOE processor register numbers 1725682Ssam */ 1825682Ssam #define SBR 0x0 /* system base register */ 1925682Ssam #define SLR 0x1 /* system length register */ 2025682Ssam #define P0BR 0x2 /* p0 base register */ 2125682Ssam #define P0LR 0x3 /* p0 length register */ 2225682Ssam #define P1BR 0x4 /* p1 base register */ 2325682Ssam #define P1LR 0x5 /* p1 length register */ 2425682Ssam #define P2BR 0x6 /* p2 base register */ 2525682Ssam #define P2LR 0x7 /* p2 length register */ 2625682Ssam #define IPL 0x8 /* interrupt priority level */ 2725682Ssam #define MME 0x9 /* memory management enable */ 2825682Ssam #define TBIA 0xa /* translation buffer invalidate all */ 2925682Ssam #define TBIS 0xb /* translation buffer invalidate single */ 3025682Ssam #define DCK 0xc /* data cache key */ 3125682Ssam #define CCK 0xd /* code cache key */ 3225682Ssam #define PCBB 0xe /* process control block base */ 3325682Ssam #define ISP 0xf /* interrupt stack pointer */ 3425682Ssam #define SIRR 0x10 /* software interrupt request */ 3525682Ssam #define SISR 0x11 /* software interrupt summary */ 3625682Ssam #define SCBB 0x12 /* system control block base */ 3725682Ssam #define KSP 0x13 /* kernelack pointer */ 3825682Ssam #define USP 0x14 /* user stack pointer */ 3925682Ssam #define CPMDCB 0x15 /* CP master DCM pointer */ 4025682Ssam #define PACC 0x17 /* purge all code cache */ 4125682Ssam #define P1DC 0x18 /* purge one data cache */ 4225682Ssam #define PADC 0x19 /* purge all data cache */ 4325682Ssam #define HISR 0x1a /* hardware interrupt summery register */ 4425682Ssam #define DCR 0x1b /* diagnostic control register */ 4525682Ssam #define PDCS 0x1c /* purge data cache slot */ 46*52626Ssklower #endif /* !_MTPR_H_ */ 47