1*30230Ssam /* if_enpreg.h 1.2 86/11/29 */ 229649Ssam 329649Ssam /* Copyright (c) 1984 by Communication Machinery Corporation 429649Ssam * 529649Ssam * This file contains material which is proprietary to 629649Ssam * Communication Machinery Corporation (CMC) and which 729649Ssam * may not be divulged without the written permission 829649Ssam * of CMC. 929649Ssam * 1029649Ssam * ENP-10 Ram Definition 1129649Ssam * 1229649Ssam * 3/15/85 Jon Phares 1329649Ssam * Update 7/10/85 S. Holmgren 1429649Ssam * ENP-10 update 7/21/85 J. Mullen 1529649Ssam * ENP-20 update 8/11/85 J. Mullen 1629649Ssam * Mods for CCI TAHOE system 8/14/85 J. Mullen 1729649Ssam */ 1829649Ssam 1929649Ssam #define K *1024 2029649Ssam 21*30230Ssam struct ether_addr { 2229649Ssam u_char ea_addr[6]; 2329649Ssam }; 2429649Ssam 25*30230Ssam typedef struct ethlist { 2629649Ssam int e_listsize; /* active addr entries */ 27*30230Ssam struct ether_addr e_baseaddr; /* addr lance is working with */ 28*30230Ssam struct ether_addr e_addrs[16]; /* possible addresses */ 2929649Ssam } ETHLIST; 3029649Ssam 31*30230Ssam typedef struct { 32*30230Ssam u_long e_xmit_successful; /* Successful transmissions */ 33*30230Ssam u_long e_mult_retry; /* multiple retries on xmit */ 34*30230Ssam u_long e_one_retry; /* single retries */ 35*30230Ssam u_long e_fail_retry; /* too many retries */ 36*30230Ssam u_long e_deferrals; /* xmit delayed 'cuz cable busy */ 37*30230Ssam u_long e_xmit_buff_err; /* xmit data chaining failed -- 3829649Ssam "can't happen" */ 39*30230Ssam u_long e_silo_underrun; /* transmit data fetch failed */ 40*30230Ssam u_long e_late_coll; /* collision after xmit */ 41*30230Ssam u_long e_lost_carrier; 42*30230Ssam u_long e_babble; /* xmit length > 1518 */ 43*30230Ssam u_long e_collision; 44*30230Ssam u_long e_xmit_mem_err; 45*30230Ssam u_long e_rcv_successful; /* good receptions */ 46*30230Ssam u_long e_rcv_missed; /* no recv buff available */ 47*30230Ssam u_long e_crc_err; /* checksum failed */ 48*30230Ssam u_long e_frame_err; /* crc error & data length != 0 mod 8 */ 49*30230Ssam u_long e_rcv_buff_err; /* rcv data chain failure -- 5029649Ssam "can't happen" */ 51*30230Ssam u_long e_silo_overrun; /* receive data store failed */ 52*30230Ssam u_long e_rcv_mem_err; 5329649Ssam } ENPSTAT; 5429649Ssam 55*30230Ssam typedef struct RING { 5629649Ssam short r_rdidx; 5729649Ssam short r_wrtidx; 5829649Ssam short r_size; 5929649Ssam short r_pad; 6029649Ssam int r_slot[1]; 6129649Ssam } RING; 6229649Ssam 63*30230Ssam typedef struct RING32 { 6429649Ssam short r_rdidx; 6529649Ssam short r_wrtidx; 6629649Ssam short r_size; 6729649Ssam short r_pad; /* to make VAXen happy */ 68*30230Ssam int r_slot[32]; 6929649Ssam } RING32; 7029649Ssam 7129649Ssam /* 72*30230Ssam * ENP Ram data layout 7329649Ssam */ 7429649Ssam 75*30230Ssam /* 76*30230Ssam * Note: paged window (4 K) is identity mapped by ENP kernel to provide 77*30230Ssam * 124 K contiguous RAM (as reflected in RAM_SIZE) 78*30230Ssam */ 79*30230Ssam #define RAM_WINDOW (128 K) 80*30230Ssam #define IOACCESS_WINDOW (512) 81*30230Ssam #define FIXED_WINDOW (RAM_WINDOW - IOACCESS_WINDOW) 82*30230Ssam #define RAMROM_SWAP (4 K) 83*30230Ssam #define RAM_SIZE (FIXED_WINDOW - RAMROM_SWAP) 84*30230Ssam 85*30230Ssam #define HOST_RAMSIZE (48 K) 86*30230Ssam #define ENP_RAMSIZE (20 K) 87*30230Ssam 88*30230Ssam typedef struct iow20 { 89*30230Ssam char pad0; 90*30230Ssam char hst2enp_interrupt; 91*30230Ssam char pad1[510]; 92*30230Ssam } iow20; 93*30230Ssam 94*30230Ssam struct enpdevice { 9529649Ssam #ifdef notdef 9629649Ssam char enp_ram_rom[4 K]; 9729649Ssam #endif notdef 9829649Ssam union { 9929649Ssam char all_ram[RAM_SIZE]; 10029649Ssam struct { 101*30230Ssam u_int t_go; 102*30230Ssam u_int t_pstart; 10329649Ssam } t; 10429649Ssam struct { 10529649Ssam char nram[RAM_SIZE - (HOST_RAMSIZE + ENP_RAMSIZE)]; 10629649Ssam char hram[HOST_RAMSIZE]; 10729649Ssam char kram[ENP_RAMSIZE]; 10829649Ssam } u_ram; 109*30230Ssam struct { 110*30230Ssam char pad7[0x100]; /* starts 0x1100 - 0x2000 */ 11129649Ssam short e_enpstate; /* 1102 */ 11229649Ssam short e_enpmode; /* 1104 */ 11329649Ssam int e_enpbase; /* 1104 */ 11429649Ssam int e_enprun; /* 1108 */ 115*30230Ssam u_short e_intrvec; 116*30230Ssam u_short e_dummy[3]; 11729649Ssam RING32 h_toenp; /* 110C */ 11829649Ssam RING32 h_hostfree; 11929649Ssam RING32 e_tohost; 12029649Ssam RING32 e_enpfree; 12129649Ssam ENPSTAT e_stat; 12229649Ssam ETHLIST e_netaddr; 12329649Ssam } iface; 12429649Ssam } enp_u; 12529649Ssam iow20 enp_iow; 126*30230Ssam }; 12729649Ssam 12829649Ssam #define enp_ram enp_u.all_ram 12929649Ssam #define enp_nram enp_u.u_ram.nram 13029649Ssam #define enp_hram enp_u.u_ram.hram 13129649Ssam #define enp_kram enp_u.u_ram.kram 13229649Ssam #define enp_go enp_u.t.t_go 13329649Ssam #define enp_prog_start enp_u.t.t_pstart 13429649Ssam #define enp_intrvec enp_u.iface.e_intrvec 13529649Ssam #define enp_state enp_u.iface.e_enpstate 13629649Ssam #define enp_mode enp_u.iface.e_enpmode 13729649Ssam #define enp_base enp_u.iface.e_enpbase 13829649Ssam #define enp_enprun enp_u.iface.e_enprun 13929649Ssam #define enp_toenp enp_u.iface.h_toenp 14029649Ssam #define enp_hostfree enp_u.iface.h_hostfree 14129649Ssam #define enp_tohost enp_u.iface.e_tohost 14229649Ssam #define enp_enpfree enp_u.iface.e_enpfree 14329649Ssam #define enp_freembuf enp_u.iface.h_freembuf 14429649Ssam #define enp_stat enp_u.iface.e_stat 14529649Ssam #define enp_addr enp_u.iface.e_netaddr 14629649Ssam 147*30230Ssam #define ENPVAL 0xff /* enp_iow.hst2enp_interrupt poke value */ 148*30230Ssam #define RESETVAL 0x00 /* enp_iow.enp2hst_clear_intr poke value */ 14929649Ssam 150*30230Ssam #define INTR_ENP(addr) (addr->enp_iow.hst2enp_interrupt = ENPVAL) 15129649Ssam 15229649Ssam #if ENP == 30 153*30230Ssam #define ACK_ENP_INTR(addr) (addr->enp_iow.enp2hst_clear_intr = RESETVAL) 15429649Ssam #define IS_ENP_INTR(addr) (addr->enp_iow.enp2hst_clear_intr&0x80) 155*30230Ssam #else 15629649Ssam #define ACK_ENP_INTR(addr) 157*30230Ssam #define IS_ENP_INTR(addr) (1) 15829649Ssam #endif ENP == 30 15929649Ssam 16029649Ssam #ifdef notdef 161*30230Ssam #define RESET_ENP(addr) (addr->enp_iow.hst2enp_reset = 01) 162*30230Ssam #else 16329649Ssam #define RESET_ENP(addr) 16429649Ssam #endif notdef 16529649Ssam 16629649Ssam #ifdef TAHOE 167*30230Ssam #define ENP_GO(addr,start) { \ 168*30230Ssam int v = start; \ 169*30230Ssam enpcopy(&v, &addr->enp_prog_start, sizeof(v) ); \ 170*30230Ssam v = 0x80800000; \ 171*30230Ssam enpcopy( &v, &addr->enp_go, sizeof(v) ); \ 172*30230Ssam } 17329649Ssam #else 174*30230Ssam #define ENP_GO(addr,start,intvec ) { \ 175*30230Ssam addr->enp_prog_start = (u_int)(start); \ 176*30230Ssam addr->enp_intrvec = (u_short) intvec; \ 177*30230Ssam addr->enp_go = 0x80800000; \ 178*30230Ssam } 17929649Ssam #endif TAHOE 18029649Ssam 18129649Ssam /* 182*30230Ssam * State bits 18329649Ssam */ 18429649Ssam #define S_ENPRESET 01 /* enp is in reset state */ 18529649Ssam #define S_ENPRUN 02 /* enp is in run state */ 18629649Ssam 18729649Ssam /* 188*30230Ssam * Mode bits 18929649Ssam */ 190*30230Ssam #define E_SWAP16 0x1 /* swap two octets within 16 */ 191*30230Ssam #define E_SWAP32 0x2 /* swap 16s within 32 */ 192*30230Ssam #define E_SWAPRD 0x4 /* swap on read */ 193*30230Ssam #define E_SWAPWRT 0x8 /* swap on write */ 194*30230Ssam #define E_DMA 0x10 /* enp does data moving */ 19529649Ssam 196*30230Ssam #define E_EXAM_LIST 0x80000000 /* enp should examine addrlist */ 197*30230Ssam #define E_ADDR_SUPP 0x40000000 /* enp should use supplied addr */ 19829649Ssam 19929649Ssam /* 200*30230Ssam * Download ioctl definitions 20129649Ssam */ 202*30230Ssam #define ENPIOGO _IO(S,1) /* start the enp */ 203*30230Ssam #define ENPIORESET _IO(S,2) /* reset the enp */ 20429649Ssam 20529649Ssam /* 206*30230Ssam * The ENP Data Buffer Structure 20729649Ssam */ 208*30230Ssam typedef struct BCB { 209*30230Ssam struct BCB *b_link; 21029649Ssam short b_stat; 21129649Ssam short b_len; 21229649Ssam char *b_addr; 21329649Ssam short b_msglen; 21429649Ssam short b_reserved; 215*30230Ssam } BCB; 216