1*34405Skarels /* 2*34405Skarels * @(#)if_acereg.h 7.1 (Berkeley) 05/21/88 3*34405Skarels */ 424008Ssam 524008Ssam /* 624008Ssam * VERSAbus ACC ethernet controller definitions 724008Ssam */ 824008Ssam 924008Ssam /* 1024008Ssam * Register definitions 1124008Ssam */ 1224008Ssam struct acedevice { 1324008Ssam short station[6]; /* station address */ 1424008Ssam short bcastena[2]; /* broadcast enable */ 1524008Ssam short hash[8]; /* multicast hash codes */ 1624008Ssam short csr; /* control and status register */ 1724008Ssam short tseg; /* current transmit segment # */ 1824008Ssam short rseg; /* current receive segment # */ 1924008Ssam short segb; /* segment boundary register */ 2024008Ssam short lrf; /* lost receive frame counter */ 2124008Ssam short ivct; /* interrupt vector register */ 2224008Ssam short resv; /* reserved for future use */ 2324008Ssam short fcoll; /* force collision register */ 2424008Ssam }; 2524008Ssam 2624008Ssam /* 2724008Ssam * Transmit segment in dual ported ram. 2824008Ssam */ 2924008Ssam struct tx_segment { 3024008Ssam short tx_csr; /* packet status */ 3124008Ssam char tx_data[2014]; 3224008Ssam short tx_backoff[16]; /* random backoff counters */ 3324008Ssam }; 3424008Ssam 3524008Ssam /* 3624008Ssam * Receive segment in dual ported ram. 3724008Ssam */ 3824008Ssam struct rx_segment { 3924008Ssam short rx_csr; /* packet status */ 4024008Ssam char rx_data[2046]; 4124008Ssam }; 4224008Ssam 4324008Ssam /* 4424008Ssam * ACC statistics block. 4524008Ssam */ 4624008Ssam struct ace_stats { 4724008Ssam int rx_datagrams; /* valid packets received */ 4824008Ssam int rx_crc_errors; /* CRC errors */ 4924008Ssam int rx_overruns; /* packets too large */ 5024008Ssam int rx_underruns; /* packets too small */ 5124008Ssam int rx_align_errors; /* packets w/ odd byte count */ 5224008Ssam int rx_reserved; 5324008Ssam int rx_busy; /* recv segment filled */ 5424008Ssam int rx_mbuf; /* out of mbufs */ 5524008Ssam int rx_oddoff; /* odd offset in mbuf */ 5624008Ssam int rx_rintcnt; /* recvr interrupt */ 5724008Ssam 5824008Ssam int tx_datagrams; /* packets xmit'd */ 5924008Ssam int tx_retries; /* collision retries */ 6024008Ssam int tx_discarded; /* packets w/ max retries */ 6124008Ssam int tx_busy; /* xmit segment filled in acestart */ 6224008Ssam int tx_cbusy; /* xmit segment filled in acecint */ 6324008Ssam int tx_mbuf; /* total mbufs */ 6424008Ssam int tx_oddoff; /* odd offset in mbuf */ 6524008Ssam int tx_outcnt; /* calls to aceoutput */ 6624008Ssam int tx_startcnt; /* calls to acestart */ 6724008Ssam int tx_cintcnt; /* xmit's completed */ 6824008Ssam }; 6924008Ssam 7024008Ssam /* 7124008Ssam * Control status definitions. 7224008Ssam */ 7324008Ssam #define CSR_OBCENA 0x0200 /* enable xmit of odd byte count */ 7424008Ssam #define CSR_ACTIVE 0x0080 /* board active */ 7524008Ssam #define CSR_RESET 0x0040 /* reset board */ 7624008Ssam #define CSR_PROMISC 0x0020 /* enable promiscous mode */ 7724008Ssam #define CSR_CRCDIS 0x0010 /* disable CRC generation */ 7824008Ssam #define CSR_LOOP3 0x0008 /* enable loopback mode 3 */ 7924008Ssam #define CSR_LOOP2 0x0004 /* enable loopback mode 2 */ 8024008Ssam #define CSR_IENA 0x0002 /* interrupt enable */ 8124008Ssam #define CSR_GO 0x0001 /* enable micro-engine */ 8224008Ssam 8324008Ssam #define ACE_CSRBITS \ 8424008Ssam "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO" 8524008Ssam /* 8624008Ssam * Transmit packet status definitions. 8724008Ssam */ 8824008Ssam #define TCS_TBFULL (short)0x8000 /* buffer filled, send it */ 8924008Ssam #define TCS_TBC (short)0x07FF /* byte count */ 9024008Ssam #define TCS_TBMT (short)0x8000 /* buffer empty */ 9124008Ssam #define TCS_RTFAIL (short)0x4000 /* retries failed */ 9224008Ssam #define TCS_RTC (short)0x000F /* collision retry mask */ 9324008Ssam 9424008Ssam /* 9524008Ssam * Receive packet status definitions. 9624008Ssam */ 9724008Ssam #define RCS_RBMT 0x8000 /* buffer ready for recv */ 9824008Ssam #define RCS_RBFULL 0x8000 /* buffer full, take data */ 9924008Ssam #define RCS_ROVRN 0x4000 /* overrun error */ 10024008Ssam #define RCS_RCRC 0x2000 /* CRC error */ 10124008Ssam #define RCS_RODD 0x1000 /* odd byte count error */ 10224008Ssam #define RCS_RBC 0x07FF /* byte count mask */ 10324008Ssam 10424008Ssam #define ACE_RCSBITS "\20\20RBFULL\17ROVRN\16RCSR\15RODD" 10524008Ssam 10624008Ssam #define CRC_SIZE 4 /* number of bytes in a rx seg's CRC */ 10724008Ssam #define RCW_SIZE 2 /* number of bytes in a rx seg's csr */ 10824008Ssam #define SEG_MAX 15 /* largest valid segment number */ 10924008Ssam #define ET_MINLEN 64 /* min frame size */ 11024008Ssam #define ET_MAXLEN 1514 /* max frame size w/o CRC & RCW */ 111