1*24008Ssam /* if_acereg.h 1.1 85/07/21 */ 2*24008Ssam 3*24008Ssam /* 4*24008Ssam * VERSAbus ACC ethernet controller definitions 5*24008Ssam */ 6*24008Ssam 7*24008Ssam /* 8*24008Ssam * Register definitions 9*24008Ssam */ 10*24008Ssam struct acedevice { 11*24008Ssam short station[6]; /* station address */ 12*24008Ssam short bcastena[2]; /* broadcast enable */ 13*24008Ssam short hash[8]; /* multicast hash codes */ 14*24008Ssam short csr; /* control and status register */ 15*24008Ssam short tseg; /* current transmit segment # */ 16*24008Ssam short rseg; /* current receive segment # */ 17*24008Ssam short segb; /* segment boundary register */ 18*24008Ssam short lrf; /* lost receive frame counter */ 19*24008Ssam short ivct; /* interrupt vector register */ 20*24008Ssam short resv; /* reserved for future use */ 21*24008Ssam short fcoll; /* force collision register */ 22*24008Ssam }; 23*24008Ssam 24*24008Ssam /* 25*24008Ssam * Transmit segment in dual ported ram. 26*24008Ssam */ 27*24008Ssam struct tx_segment { 28*24008Ssam short tx_csr; /* packet status */ 29*24008Ssam char tx_data[2014]; 30*24008Ssam short tx_backoff[16]; /* random backoff counters */ 31*24008Ssam }; 32*24008Ssam 33*24008Ssam /* 34*24008Ssam * Receive segment in dual ported ram. 35*24008Ssam */ 36*24008Ssam struct rx_segment { 37*24008Ssam short rx_csr; /* packet status */ 38*24008Ssam char rx_data[2046]; 39*24008Ssam }; 40*24008Ssam 41*24008Ssam /* 42*24008Ssam * ACC statistics block. 43*24008Ssam */ 44*24008Ssam struct ace_stats { 45*24008Ssam int rx_datagrams; /* valid packets received */ 46*24008Ssam int rx_crc_errors; /* CRC errors */ 47*24008Ssam int rx_overruns; /* packets too large */ 48*24008Ssam int rx_underruns; /* packets too small */ 49*24008Ssam int rx_align_errors; /* packets w/ odd byte count */ 50*24008Ssam int rx_reserved; 51*24008Ssam int rx_busy; /* recv segment filled */ 52*24008Ssam int rx_mbuf; /* out of mbufs */ 53*24008Ssam int rx_oddoff; /* odd offset in mbuf */ 54*24008Ssam int rx_rintcnt; /* recvr interrupt */ 55*24008Ssam 56*24008Ssam int tx_datagrams; /* packets xmit'd */ 57*24008Ssam int tx_retries; /* collision retries */ 58*24008Ssam int tx_discarded; /* packets w/ max retries */ 59*24008Ssam int tx_busy; /* xmit segment filled in acestart */ 60*24008Ssam int tx_cbusy; /* xmit segment filled in acecint */ 61*24008Ssam int tx_mbuf; /* total mbufs */ 62*24008Ssam int tx_oddoff; /* odd offset in mbuf */ 63*24008Ssam int tx_outcnt; /* calls to aceoutput */ 64*24008Ssam int tx_startcnt; /* calls to acestart */ 65*24008Ssam int tx_cintcnt; /* xmit's completed */ 66*24008Ssam }; 67*24008Ssam 68*24008Ssam /* 69*24008Ssam * Control status definitions. 70*24008Ssam */ 71*24008Ssam #define CSR_OBCENA 0x0200 /* enable xmit of odd byte count */ 72*24008Ssam #define CSR_ACTIVE 0x0080 /* board active */ 73*24008Ssam #define CSR_RESET 0x0040 /* reset board */ 74*24008Ssam #define CSR_PROMISC 0x0020 /* enable promiscous mode */ 75*24008Ssam #define CSR_CRCDIS 0x0010 /* disable CRC generation */ 76*24008Ssam #define CSR_LOOP3 0x0008 /* enable loopback mode 3 */ 77*24008Ssam #define CSR_LOOP2 0x0004 /* enable loopback mode 2 */ 78*24008Ssam #define CSR_IENA 0x0002 /* interrupt enable */ 79*24008Ssam #define CSR_GO 0x0001 /* enable micro-engine */ 80*24008Ssam 81*24008Ssam #define ACE_CSRBITS \ 82*24008Ssam "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO" 83*24008Ssam /* 84*24008Ssam * Transmit packet status definitions. 85*24008Ssam */ 86*24008Ssam #define TCS_TBFULL (short)0x8000 /* buffer filled, send it */ 87*24008Ssam #define TCS_TBC (short)0x07FF /* byte count */ 88*24008Ssam #define TCS_TBMT (short)0x8000 /* buffer empty */ 89*24008Ssam #define TCS_RTFAIL (short)0x4000 /* retries failed */ 90*24008Ssam #define TCS_RTC (short)0x000F /* collision retry mask */ 91*24008Ssam 92*24008Ssam /* 93*24008Ssam * Receive packet status definitions. 94*24008Ssam */ 95*24008Ssam #define RCS_RBMT 0x8000 /* buffer ready for recv */ 96*24008Ssam #define RCS_RBFULL 0x8000 /* buffer full, take data */ 97*24008Ssam #define RCS_ROVRN 0x4000 /* overrun error */ 98*24008Ssam #define RCS_RCRC 0x2000 /* CRC error */ 99*24008Ssam #define RCS_RODD 0x1000 /* odd byte count error */ 100*24008Ssam #define RCS_RBC 0x07FF /* byte count mask */ 101*24008Ssam 102*24008Ssam #define ACE_RCSBITS "\20\20RBFULL\17ROVRN\16RCSR\15RODD" 103*24008Ssam 104*24008Ssam #define CRC_SIZE 4 /* number of bytes in a rx seg's CRC */ 105*24008Ssam #define RCW_SIZE 2 /* number of bytes in a rx seg's csr */ 106*24008Ssam #define SEG_MAX 15 /* largest valid segment number */ 107*24008Ssam #define ET_MINLEN 64 /* min frame size */ 108*24008Ssam #define ET_MAXLEN 1514 /* max frame size w/o CRC & RCW */ 109