1*55157Storek /* 2*55157Storek * Copyright (c) 1992 The Regents of the University of California. 3*55157Storek * All rights reserved. 4*55157Storek * 5*55157Storek * This software was developed by the Computer Systems Engineering group 6*55157Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7*55157Storek * contributed to Berkeley. 8*55157Storek * 9*55157Storek * %sccs.include.redist.c% 10*55157Storek * 11*55157Storek * @(#)vaddrs.h 7.1 (Berkeley) 07/13/92 12*55157Storek * 13*55157Storek * from: $Header: vaddrs.h,v 1.2 92/07/11 11:19:25 leres Exp $ 14*55157Storek */ 15*55157Storek 16*55157Storek /* 17*55157Storek * Special (fixed) virtual addresses on the SPARC. 18*55157Storek * 19*55157Storek * IO virtual space begins at 0xfe000000 (a segment boundary) and 20*55157Storek * continues up to the DMVA edge at 0xff000000. (The upper all-1s 21*55157Storek * byte is special since some of the hardware supplies this to pad 22*55157Storek * a 24-bit address space out to 32 bits. This is a legacy of the 23*55157Storek * IBM PC AT bus, actually, just so you know who to blame.) 24*55157Storek * 25*55157Storek * We reserve several pages at the base of our IO virtual space 26*55157Storek * for `oft-used' devices which must be present anyway in order to 27*55157Storek * configure. In particular, we want the counter-timer register and 28*55157Storek * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 29*55157Storek * microtime() and the zs hardware interrupt handlers faster. 30*55157Storek * 31*55157Storek * Ideally, we should map the interrupt enable register here as well, 32*55157Storek * but that would require allocating pmegs in locore.s, so instead we 33*55157Storek * use one of the two `wasted' pages at KERNBASE+2*NBPG (see locore.s). 34*55157Storek */ 35*55157Storek 36*55157Storek #ifndef IODEV_0 37*55157Storek #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 38*55157Storek 39*55157Storek #define TIMERREG_VA (IODEV_0 + 0*NBPG) 40*55157Storek #define ZS0_VA (IODEV_0 + 1*NBPG) 41*55157Storek #define ZS1_VA (IODEV_0 + 2*NBPG) 42*55157Storek #define AUXREG_VA (IODEV_0 + 3*NBPG) 43*55157Storek #define IODEV_BASE (IODEV_0 + 4*NBPG) 44*55157Storek #define IODEV_END 0xff000000 /* 16 MB of iospace */ 45*55157Storek 46*55157Storek #define DVMA_BASE 0xfff00000 47*55157Storek #define DVMA_END 0xfffc0000 48*55157Storek 49*55157Storek #endif /* IODEV_0 */ 50