155157Storek /* 2*63323Sbostic * Copyright (c) 1992, 1993 3*63323Sbostic * The Regents of the University of California. All rights reserved. 455157Storek * 555157Storek * This software was developed by the Computer Systems Engineering group 655157Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 755157Storek * contributed to Berkeley. 855157Storek * 955504Sbostic * All advertising materials mentioning features or use of this software 1055504Sbostic * must display the following acknowledgement: 1155504Sbostic * This product includes software developed by the University of 1259249Storek * California, Lawrence Berkeley Laboratory. 1355504Sbostic * 1455157Storek * %sccs.include.redist.c% 1555157Storek * 16*63323Sbostic * @(#)vaddrs.h 8.1 (Berkeley) 06/11/93 1755157Storek * 1859249Storek * from: $Header: vaddrs.h,v 1.3 92/11/26 03:05:11 torek Exp $ 1955157Storek */ 2055157Storek 2155157Storek /* 2255157Storek * Special (fixed) virtual addresses on the SPARC. 2355157Storek * 2455157Storek * IO virtual space begins at 0xfe000000 (a segment boundary) and 2555157Storek * continues up to the DMVA edge at 0xff000000. (The upper all-1s 2655157Storek * byte is special since some of the hardware supplies this to pad 2755157Storek * a 24-bit address space out to 32 bits. This is a legacy of the 2855157Storek * IBM PC AT bus, actually, just so you know who to blame.) 2955157Storek * 3055157Storek * We reserve several pages at the base of our IO virtual space 3155157Storek * for `oft-used' devices which must be present anyway in order to 3255157Storek * configure. In particular, we want the counter-timer register and 3355157Storek * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 3455157Storek * microtime() and the zs hardware interrupt handlers faster. 3555157Storek * 3655157Storek * Ideally, we should map the interrupt enable register here as well, 3755157Storek * but that would require allocating pmegs in locore.s, so instead we 3855157Storek * use one of the two `wasted' pages at KERNBASE+2*NBPG (see locore.s). 3955157Storek */ 4055157Storek 4155157Storek #ifndef IODEV_0 4255157Storek #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 4355157Storek 4455157Storek #define TIMERREG_VA (IODEV_0 + 0*NBPG) 4555157Storek #define ZS0_VA (IODEV_0 + 1*NBPG) 4655157Storek #define ZS1_VA (IODEV_0 + 2*NBPG) 4755157Storek #define AUXREG_VA (IODEV_0 + 3*NBPG) 4855157Storek #define IODEV_BASE (IODEV_0 + 4*NBPG) 4955157Storek #define IODEV_END 0xff000000 /* 16 MB of iospace */ 5055157Storek 5155157Storek #define DVMA_BASE 0xfff00000 5255157Storek #define DVMA_END 0xfffc0000 5355157Storek 5455157Storek #endif /* IODEV_0 */ 55