155137Storek /* 255137Storek * Copyright (c) 1992 The Regents of the University of California. 355137Storek * All rights reserved. 455137Storek * 555137Storek * This software was developed by the Computer Systems Engineering group 655137Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 755137Storek * contributed to Berkeley. 855137Storek * 9*55503Sbostic * All advertising materials mentioning features or use of this software 10*55503Sbostic * must display the following acknowledgement: 11*55503Sbostic * This product includes software developed by the University of 12*55503Sbostic * California, Lawrence Berkeley Laboratories. 13*55503Sbostic * 1455137Storek * %sccs.include.redist.c% 1555137Storek * 16*55503Sbostic * @(#)dmareg.h 7.2 (Berkeley) 07/21/92 1755137Storek * 1855137Storek * from: $Header: dmareg.h,v 1.4 92/06/17 06:59:33 torek Exp $ (LBL) 1955137Storek */ 2055137Storek 2155137Storek /* 2255137Storek * Sun-4c Sbus slot 0 DMA registers. 2355137Storek */ 2455137Storek struct dmareg { 2555137Storek u_long dma_csr; /* control/status register */ 2655137Storek u_long dma_addr; /* address (virtual: is fed to MMU) */ 2755137Storek u_long dma_bc; /* byte count (not used) */ 2855137Storek u_long dma_diag; /* diagnostic register (not used) */ 2955137Storek }; 3055137Storek 3155137Storek /* 3255137Storek * Bits in dma_csr. 3355137Storek * 3455137Storek * Notes in [brackets]: 3555137Storek * 1: not self-clearing, must be reset after being set. 3655137Storek * 2: `drain' is like Unibus `bdp purge', i.e., it tells 3755137Storek * the chip to finish up, because there is no more data 3855137Storek * going into the buffer register. Needed only in rev 3955137Storek * 1 dma chips. Self-clearing (hence write-only). 4055137Storek * 3: only in rev 1 dma chips. 4155137Storek * 4: only in rev 2 dma chips. 4255137Storek * 5: also enables scsi interrupts. 4355137Storek */ 4455137Storek #define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */ 4555137Storek #define DMAREV_1 0x8 /* device id = rev 1 DMA */ 4655137Storek #define DMAREV_2 0x9 /* device id = rev 2 DMA */ 4755137Storek 4855137Storek #define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [3] */ 4955137Storek #define DMA_NAL 0x08000000 /* next address loaded [4] (ro) */ 5055137Storek #define DMA_AL 0x04000000 /* address loaded [4] (ro) */ 5155137Storek #define DMA_ON 0x02000000 /* working [4] (ro) */ 5255137Storek #define DMA_NAE 0x01000000 /* next-address enable [4] (rw) */ 5355137Storek #define DMA_DTCI 0x00800000 /* disable DMA_TC intr [4] (rw) */ 5455137Storek #define DMA_TURBO 0x00400000 /* faster 53C90A mode [4] (rw) */ 5555137Storek #define DMA_LERR 0x00200000 /* LANCE error [4] (ro) */ 5655137Storek #define DMA_ALE 0x00100000 /* LANCE addr latch ena [4] (rw) */ 5755137Storek #define DMA_2ZERO 0x000f0000 /* unused; reads as zero [4] */ 5855137Storek #define DMA_ILACC 0x00008000 /* set for new AMD ethernet chip */ 5955137Storek #define DMA_TC 0x00004000 /* terminal count: dma_bc ran out */ 6055137Storek #define DMA_BCE 0x00002000 /* byte count enable (leave 0) */ 6155137Storek #define DMA_BO 0x00001800 /* byte offset (ro) */ 6255137Storek #define DMA_RP 0x00000400 /* request pending (ro) */ 6355137Storek #define DMA_ENA 0x00000200 /* enable the dma chip */ 6455137Storek #define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */ 6555137Storek #define DMA_RESET 0x00000080 /* reset dma chip [1] */ 6655137Storek #define DMA_DRAIN 0x00000040 /* drain buffered data [2,3] (wo) */ 6755137Storek #define DMA_ERR 0x00000040 /* slave error [4] (ro) */ 6855137Storek #define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [4] (wo) */ 6955137Storek #define DMA_IE 0x00000010 /* interrupt enable [4,5] */ 7055137Storek #define DMA_PC 0x0000000c /* bytes in pack reg (ro) */ 7155137Storek #define DMA_EP 0x00000002 /* error pending (ro) */ 7255137Storek #define DMA_IP 0x00000001 /* interrupt pending (ro) */ 7355137Storek 7455137Storek #define DMA_BITS \ 7555137Storek "\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\ 7655137Storek \20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN/ERR\6FLUSH\5IE\2EP\1IP" 7755137Storek 7855137Storek /* DMA_BYTE turns the DMA_BO field into a byte index */ 7955137Storek #define DMA_BYTE(csr) (((csr) >> 11) & 3) 8055137Storek 8155137Storek /* DMA_NPACK turns the DMA_PC field into a byte count */ 8255137Storek #define DMA_NPACK(csr) (((csr) >> 2) & 3) 8355137Storek 8455137Storek /* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */ 8555137Storek #define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP)) 86