1*55137Storek /* 2*55137Storek * Copyright (c) 1992 The Regents of the University of California. 3*55137Storek * All rights reserved. 4*55137Storek * 5*55137Storek * This software was developed by the Computer Systems Engineering group 6*55137Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7*55137Storek * contributed to Berkeley. 8*55137Storek * 9*55137Storek * %sccs.include.redist.c% 10*55137Storek * 11*55137Storek * @(#)dmareg.h 7.1 (Berkeley) 07/13/92 12*55137Storek * 13*55137Storek * from: $Header: dmareg.h,v 1.4 92/06/17 06:59:33 torek Exp $ (LBL) 14*55137Storek */ 15*55137Storek 16*55137Storek /* 17*55137Storek * Sun-4c Sbus slot 0 DMA registers. 18*55137Storek */ 19*55137Storek struct dmareg { 20*55137Storek u_long dma_csr; /* control/status register */ 21*55137Storek u_long dma_addr; /* address (virtual: is fed to MMU) */ 22*55137Storek u_long dma_bc; /* byte count (not used) */ 23*55137Storek u_long dma_diag; /* diagnostic register (not used) */ 24*55137Storek }; 25*55137Storek 26*55137Storek /* 27*55137Storek * Bits in dma_csr. 28*55137Storek * 29*55137Storek * Notes in [brackets]: 30*55137Storek * 1: not self-clearing, must be reset after being set. 31*55137Storek * 2: `drain' is like Unibus `bdp purge', i.e., it tells 32*55137Storek * the chip to finish up, because there is no more data 33*55137Storek * going into the buffer register. Needed only in rev 34*55137Storek * 1 dma chips. Self-clearing (hence write-only). 35*55137Storek * 3: only in rev 1 dma chips. 36*55137Storek * 4: only in rev 2 dma chips. 37*55137Storek * 5: also enables scsi interrupts. 38*55137Storek */ 39*55137Storek #define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */ 40*55137Storek #define DMAREV_1 0x8 /* device id = rev 1 DMA */ 41*55137Storek #define DMAREV_2 0x9 /* device id = rev 2 DMA */ 42*55137Storek 43*55137Storek #define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [3] */ 44*55137Storek #define DMA_NAL 0x08000000 /* next address loaded [4] (ro) */ 45*55137Storek #define DMA_AL 0x04000000 /* address loaded [4] (ro) */ 46*55137Storek #define DMA_ON 0x02000000 /* working [4] (ro) */ 47*55137Storek #define DMA_NAE 0x01000000 /* next-address enable [4] (rw) */ 48*55137Storek #define DMA_DTCI 0x00800000 /* disable DMA_TC intr [4] (rw) */ 49*55137Storek #define DMA_TURBO 0x00400000 /* faster 53C90A mode [4] (rw) */ 50*55137Storek #define DMA_LERR 0x00200000 /* LANCE error [4] (ro) */ 51*55137Storek #define DMA_ALE 0x00100000 /* LANCE addr latch ena [4] (rw) */ 52*55137Storek #define DMA_2ZERO 0x000f0000 /* unused; reads as zero [4] */ 53*55137Storek #define DMA_ILACC 0x00008000 /* set for new AMD ethernet chip */ 54*55137Storek #define DMA_TC 0x00004000 /* terminal count: dma_bc ran out */ 55*55137Storek #define DMA_BCE 0x00002000 /* byte count enable (leave 0) */ 56*55137Storek #define DMA_BO 0x00001800 /* byte offset (ro) */ 57*55137Storek #define DMA_RP 0x00000400 /* request pending (ro) */ 58*55137Storek #define DMA_ENA 0x00000200 /* enable the dma chip */ 59*55137Storek #define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */ 60*55137Storek #define DMA_RESET 0x00000080 /* reset dma chip [1] */ 61*55137Storek #define DMA_DRAIN 0x00000040 /* drain buffered data [2,3] (wo) */ 62*55137Storek #define DMA_ERR 0x00000040 /* slave error [4] (ro) */ 63*55137Storek #define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [4] (wo) */ 64*55137Storek #define DMA_IE 0x00000010 /* interrupt enable [4,5] */ 65*55137Storek #define DMA_PC 0x0000000c /* bytes in pack reg (ro) */ 66*55137Storek #define DMA_EP 0x00000002 /* error pending (ro) */ 67*55137Storek #define DMA_IP 0x00000001 /* interrupt pending (ro) */ 68*55137Storek 69*55137Storek #define DMA_BITS \ 70*55137Storek "\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\ 71*55137Storek \20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN/ERR\6FLUSH\5IE\2EP\1IP" 72*55137Storek 73*55137Storek /* DMA_BYTE turns the DMA_BO field into a byte index */ 74*55137Storek #define DMA_BYTE(csr) (((csr) >> 11) & 3) 75*55137Storek 76*55137Storek /* DMA_NPACK turns the DMA_PC field into a byte count */ 77*55137Storek #define DMA_NPACK(csr) (((csr) >> 2) & 3) 78*55137Storek 79*55137Storek /* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */ 80*55137Storek #define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP)) 81