155137Storek /* 2*63322Sbostic * Copyright (c) 1992, 1993 3*63322Sbostic * The Regents of the University of California. All rights reserved. 455137Storek * 555137Storek * This software was developed by the Computer Systems Engineering group 655137Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 755137Storek * contributed to Berkeley. 855137Storek * 955503Sbostic * All advertising materials mentioning features or use of this software 1055503Sbostic * must display the following acknowledgement: 1155503Sbostic * This product includes software developed by the University of 1259213Storek * California, Lawrence Berkeley Laboratory. 1355503Sbostic * 1455137Storek * %sccs.include.redist.c% 1555137Storek * 16*63322Sbostic * @(#)dmareg.h 8.1 (Berkeley) 06/11/93 1755137Storek * 1859326Storek * from: $Header: dmareg.h,v 1.6 93/04/27 14:39:17 torek Exp $ (LBL) 1955137Storek */ 2055137Storek 2155137Storek /* 2255137Storek * Sun-4c Sbus slot 0 DMA registers. 2359326Storek * 2459326Storek * Note that the dma_addr on the rev 1 gate array cannot increment 2559326Storek * across a 16 MB boundary (the counter is only 24 bits wide; the 2659326Storek * top 8 bits are simply latched). 2755137Storek */ 2855137Storek struct dmareg { 2955137Storek u_long dma_csr; /* control/status register */ 3055137Storek u_long dma_addr; /* address (virtual: is fed to MMU) */ 3155137Storek u_long dma_bc; /* byte count (not used) */ 3255137Storek u_long dma_diag; /* diagnostic register (not used) */ 3355137Storek }; 3455137Storek 3555137Storek /* 3655137Storek * Bits in dma_csr. 3759326Storek * DMA chip revision numbers are confusing (rev 3 = `DMA2'?!). 3859326Storek * Not my fault; we just live with what they give us.... 3955137Storek * 4055137Storek * Notes in [brackets]: 4159326Storek * 1: used this way in rev 1 (`DMA') chips. 4259326Storek * 2: used this way in rev 2 (`DMA+') chips. 4359326Storek * 3: used this way in rev 3 (`DMA2') chips. 4459326Storek * R: not self-clearing, must be reset after being set. 4559326Storek * D: `drain' is like Unibus `bdp purge', i.e., it tells 4655137Storek * the chip to finish up, because there is no more data 4759326Storek * going into the buffer register. Supposed to be needed 4859326Storek * only in rev 1, but apparently needed or harmless in all 4959326Storek * revs. Self-clearing (hence write-only). 5059326Storek * I: also enables scsi interrupts. 5155137Storek */ 5255137Storek #define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */ 5359326Storek #define DMAREV_1 0x8 /* rev 1 DMA gate array */ 5459326Storek #define DMAREV_2 0x9 /* rev 2 DMA gate array (`DMA+') */ 5559326Storek #define DMAREV_3 0xa /* rev 3 DMA gate array (`DMA2') */ 5655137Storek 5759326Storek #define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [1] */ 5859326Storek #define DMA_NAL 0x08000000 /* next address loaded [2] (ro) */ 5959326Storek #define DMA_AL 0x04000000 /* address loaded [2] (ro) */ 6059326Storek #define DMA_ON 0x02000000 /* working [2] (ro) */ 6159326Storek #define DMA_NAE 0x01000000 /* next-address enable [2] (rw) */ 6259326Storek #define DMA_DTCI 0x00800000 /* disable DMA_TC intr [2] (rw) */ 6359326Storek #define DMA_TURBO 0x00400000 /* faster 53C90A mode [2] (rw) */ 6459326Storek #define DMA_LERR 0x00200000 /* LANCE error [2] (ro) */ 6559326Storek #define DMA_TWOCYCLE 0x00200000 /* two cycle mode [3] (rw?) */ 6659326Storek #define DMA_ALE 0x00100000 /* LANCE addr latch ena [2] (rw) */ 6759326Storek #define DMA_2ZERO 0x000f0000 /* unused; reads as zero [2] */ 6859326Storek #define DMA_BURSTMASK 0x000c0000 /* burst mode mask [3] */ 6959326Storek #define DMA_BURST16 0x00000000 /* 16-byte bursts (default) */ 7059326Storek #define DMA_BURST32 0x00040000 /* 32-byte bursts */ 7159326Storek #define DMA_BURST0 0x00080000 /* no bursts */ 7259326Storek #define DMA_ILACC 0x00008000 /* for new AMD ethernet chip [1,2] */ 7359326Storek #define DMA_TC 0x00004000 /* terminal cnt: dma_bc ran out [1,2] */ 7455137Storek #define DMA_BCE 0x00002000 /* byte count enable (leave 0) */ 7559326Storek #define DMA_BO 0x00001800 /* byte offset [1] (ro) */ 7659326Storek #define DMA_RP 0x00000400 /* busy, plz don't flush [1] (ro) */ 7755137Storek #define DMA_ENA 0x00000200 /* enable the dma chip */ 7855137Storek #define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */ 7959326Storek #define DMA_RESET 0x00000080 /* reset dma chip [R] */ 8059326Storek #define DMA_DRAIN 0x00000040 /* drain buffered data [D,1] (wo) */ 8159326Storek #define DMA_SLAVEERR 0x00000040 /* slave error [2,3] (ro) */ 8259326Storek #define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [2,3] (wo) */ 8359326Storek #define DMA_IE 0x00000010 /* interrupt enable [2,3,I] */ 8459326Storek #define DMA_PC 0x0000000c /* bytes in pack reg [1] (ro) */ 8559326Storek #define DMA_DRAINING 0x0000000c /* nonzero => draining [2,3] (ro) */ 8655137Storek #define DMA_EP 0x00000002 /* error pending (ro) */ 8755137Storek #define DMA_IP 0x00000001 /* interrupt pending (ro) */ 8855137Storek 8959326Storek #define DMA_REV1_BITS \ 9059326Storek "\20\20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN\2EP\1IP" 9159326Storek 9259326Storek /* Look ma, second system syndrome! */ 9359326Storek #define DMA_REV2_BITS \ 9455137Storek "\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\ 9559326Storek \20ILACC\17TC\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP" 9655137Storek 9759326Storek /* (Note how most of the crap has been discarded now.) */ 9859326Storek #define DMA_REV3_BITS \ 9959326Storek "\20\26TWOCYCLE\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP" 10059326Storek 10155137Storek /* DMA_BYTE turns the DMA_BO field into a byte index */ 10255137Storek #define DMA_BYTE(csr) (((csr) >> 11) & 3) 10355137Storek 10455137Storek /* DMA_NPACK turns the DMA_PC field into a byte count */ 10555137Storek #define DMA_NPACK(csr) (((csr) >> 2) & 3) 10655137Storek 10755137Storek /* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */ 10855137Storek #define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP)) 109