1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)fsr.h 7.1 (Berkeley) 07/13/92 12 * 13 * from: $Header: fsr.h,v 1.5 92/06/17 06:10:18 torek Exp $ 14 */ 15 16 #ifndef _MACHINE_FSR_H_ 17 #define _MACHINE_FSR_H_ 18 19 /* 20 * Bits in FSR. 21 */ 22 #define FSR_RD 0xc0000000 /* rounding direction */ 23 #define FSR_RD_RN 0 /* round to nearest */ 24 #define FSR_RD_RZ 1 /* round towards 0 */ 25 #define FSR_RD_RP 2 /* round towards +inf */ 26 #define FSR_RD_RM 3 /* round towards -inf */ 27 #define FSR_RD_SHIFT 30 28 #define FSR_RD_MASK 0x03 29 30 #define FSR_RP 0x30000000 /* extended rounding precision */ 31 #define FSR_RP_X 0 /* extended stays extended */ 32 #define FSR_RP_S 1 /* extended => single */ 33 #define FSR_RP_D 2 /* extended => double */ 34 #define FSR_RP_80 3 /* extended => 80-bit */ 35 #define FSR_RP_SHIFT 28 36 #define FSR_RP_MASK 0x03 37 38 #define FSR_TEM 0x0f800000 /* trap enable mask */ 39 #define FSR_TEM_SHIFT 23 40 #define FSR_TEM_MASK 0x1f 41 42 #define FSR_NS 0x00400000 /* ``nonstandard mode'' */ 43 #define FSR_AU 0x00400000 /* aka abrupt underflow mode */ 44 #define FSR_MBZ 0x00300000 /* reserved; must be zero */ 45 46 #define FSR_VER 0x000e0000 /* version bits */ 47 #define FSR_VER_SHIFT 17 48 #define FSR_VER_MASK 0x07 49 50 #define FSR_FTT 0x0001c000 /* FP trap type */ 51 #define FSR_TT_NONE 0 /* no trap */ 52 #define FSR_TT_IEEE 1 /* IEEE exception */ 53 #define FSR_TT_UNFIN 2 /* unfinished operation */ 54 #define FSR_TT_UNIMP 3 /* unimplemented operation */ 55 #define FSR_TT_SEQ 4 /* sequence error */ 56 #define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 57 #define FSR_FTT_SHIFT 14 58 #define FSR_FTT_MASK 0x03 59 60 #define FSR_QNE 0x00002000 /* queue not empty */ 61 #define FSR_PR 0x00001000 /* partial result */ 62 63 #define FSR_FCC 0x00000c00 /* FP condition codes */ 64 #define FSR_CC_EQ 0 /* f1 = f2 */ 65 #define FSR_CC_LT 1 /* f1 < f2 */ 66 #define FSR_CC_GT 2 /* f1 > f2 */ 67 #define FSR_CC_UO 3 /* (f1,f2) unordered */ 68 #define FSR_FCC_SHIFT 10 69 #define FSR_FCC_MASK 0x03 70 71 #define FSR_AX 0x000003e0 /* accrued exceptions */ 72 #define FSR_AX_SHIFT 5 73 #define FSR_AX_MASK 0x1f 74 #define FSR_CX 0x0000001f /* current exceptions */ 75 #define FSR_CX_SHIFT 0 76 #define FSR_CX_MASK 0x1f 77 78 /* The following exceptions apply to TEM, AX, and CX. */ 79 #define FSR_NV 0x10 /* invalid operand */ 80 #define FSR_OF 0x08 /* overflow */ 81 #define FSR_UF 0x04 /* underflow */ 82 #define FSR_DZ 0x02 /* division by zero */ 83 #define FSR_NX 0x01 /* inexact result */ 84 85 #endif /* _MACHINE_FSR_H_ */ 86