1*55120Storek /* 2*55120Storek * Copyright (c) 1992 The Regents of the University of California. 3*55120Storek * All rights reserved. 4*55120Storek * 5*55120Storek * This software was developed by the Computer Systems Engineering group 6*55120Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7*55120Storek * contributed to Berkeley. 8*55120Storek * 9*55120Storek * %sccs.include.redist.c% 10*55120Storek * 11*55120Storek * @(#)fsr.h 7.1 (Berkeley) 07/13/92 12*55120Storek * 13*55120Storek * from: $Header: fsr.h,v 1.5 92/06/17 06:10:18 torek Exp $ 14*55120Storek */ 15*55120Storek 16*55120Storek #ifndef _MACHINE_FSR_H_ 17*55120Storek #define _MACHINE_FSR_H_ 18*55120Storek 19*55120Storek /* 20*55120Storek * Bits in FSR. 21*55120Storek */ 22*55120Storek #define FSR_RD 0xc0000000 /* rounding direction */ 23*55120Storek #define FSR_RD_RN 0 /* round to nearest */ 24*55120Storek #define FSR_RD_RZ 1 /* round towards 0 */ 25*55120Storek #define FSR_RD_RP 2 /* round towards +inf */ 26*55120Storek #define FSR_RD_RM 3 /* round towards -inf */ 27*55120Storek #define FSR_RD_SHIFT 30 28*55120Storek #define FSR_RD_MASK 0x03 29*55120Storek 30*55120Storek #define FSR_RP 0x30000000 /* extended rounding precision */ 31*55120Storek #define FSR_RP_X 0 /* extended stays extended */ 32*55120Storek #define FSR_RP_S 1 /* extended => single */ 33*55120Storek #define FSR_RP_D 2 /* extended => double */ 34*55120Storek #define FSR_RP_80 3 /* extended => 80-bit */ 35*55120Storek #define FSR_RP_SHIFT 28 36*55120Storek #define FSR_RP_MASK 0x03 37*55120Storek 38*55120Storek #define FSR_TEM 0x0f800000 /* trap enable mask */ 39*55120Storek #define FSR_TEM_SHIFT 23 40*55120Storek #define FSR_TEM_MASK 0x1f 41*55120Storek 42*55120Storek #define FSR_NS 0x00400000 /* ``nonstandard mode'' */ 43*55120Storek #define FSR_AU 0x00400000 /* aka abrupt underflow mode */ 44*55120Storek #define FSR_MBZ 0x00300000 /* reserved; must be zero */ 45*55120Storek 46*55120Storek #define FSR_VER 0x000e0000 /* version bits */ 47*55120Storek #define FSR_VER_SHIFT 17 48*55120Storek #define FSR_VER_MASK 0x07 49*55120Storek 50*55120Storek #define FSR_FTT 0x0001c000 /* FP trap type */ 51*55120Storek #define FSR_TT_NONE 0 /* no trap */ 52*55120Storek #define FSR_TT_IEEE 1 /* IEEE exception */ 53*55120Storek #define FSR_TT_UNFIN 2 /* unfinished operation */ 54*55120Storek #define FSR_TT_UNIMP 3 /* unimplemented operation */ 55*55120Storek #define FSR_TT_SEQ 4 /* sequence error */ 56*55120Storek #define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 57*55120Storek #define FSR_FTT_SHIFT 14 58*55120Storek #define FSR_FTT_MASK 0x03 59*55120Storek 60*55120Storek #define FSR_QNE 0x00002000 /* queue not empty */ 61*55120Storek #define FSR_PR 0x00001000 /* partial result */ 62*55120Storek 63*55120Storek #define FSR_FCC 0x00000c00 /* FP condition codes */ 64*55120Storek #define FSR_CC_EQ 0 /* f1 = f2 */ 65*55120Storek #define FSR_CC_LT 1 /* f1 < f2 */ 66*55120Storek #define FSR_CC_GT 2 /* f1 > f2 */ 67*55120Storek #define FSR_CC_UO 3 /* (f1,f2) unordered */ 68*55120Storek #define FSR_FCC_SHIFT 10 69*55120Storek #define FSR_FCC_MASK 0x03 70*55120Storek 71*55120Storek #define FSR_AX 0x000003e0 /* accrued exceptions */ 72*55120Storek #define FSR_AX_SHIFT 5 73*55120Storek #define FSR_AX_MASK 0x1f 74*55120Storek #define FSR_CX 0x0000001f /* current exceptions */ 75*55120Storek #define FSR_CX_SHIFT 0 76*55120Storek #define FSR_CX_MASK 0x1f 77*55120Storek 78*55120Storek /* The following exceptions apply to TEM, AX, and CX. */ 79*55120Storek #define FSR_NV 0x10 /* invalid operand */ 80*55120Storek #define FSR_OF 0x08 /* overflow */ 81*55120Storek #define FSR_UF 0x04 /* underflow */ 82*55120Storek #define FSR_DZ 0x02 /* division by zero */ 83*55120Storek #define FSR_NX 0x01 /* inexact result */ 84*55120Storek 85*55120Storek #endif /* _MACHINE_FSR_H_ */ 86