155120Storek /* 2*63320Sbostic * Copyright (c) 1992, 1993 3*63320Sbostic * The Regents of the University of California. All rights reserved. 455120Storek * 555120Storek * This software was developed by the Computer Systems Engineering group 655120Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 755120Storek * contributed to Berkeley. 855120Storek * 955501Sbostic * All advertising materials mentioning features or use of this software 1055501Sbostic * must display the following acknowledgement: 1155501Sbostic * This product includes software developed by the University of 1259209Storek * California, Lawrence Berkeley Laboratory. 1355501Sbostic * 1455120Storek * %sccs.include.redist.c% 1555120Storek * 16*63320Sbostic * @(#)fsr.h 8.1 (Berkeley) 06/11/93 1755120Storek * 1859209Storek * from: $Header: fsr.h,v 1.6 92/11/26 02:04:36 torek Exp $ 1955120Storek */ 2055120Storek 2155120Storek #ifndef _MACHINE_FSR_H_ 2255120Storek #define _MACHINE_FSR_H_ 2355120Storek 2455120Storek /* 2555120Storek * Bits in FSR. 2655120Storek */ 2755120Storek #define FSR_RD 0xc0000000 /* rounding direction */ 2855120Storek #define FSR_RD_RN 0 /* round to nearest */ 2955120Storek #define FSR_RD_RZ 1 /* round towards 0 */ 3055120Storek #define FSR_RD_RP 2 /* round towards +inf */ 3155120Storek #define FSR_RD_RM 3 /* round towards -inf */ 3255120Storek #define FSR_RD_SHIFT 30 3355120Storek #define FSR_RD_MASK 0x03 3455120Storek 3555120Storek #define FSR_RP 0x30000000 /* extended rounding precision */ 3655120Storek #define FSR_RP_X 0 /* extended stays extended */ 3755120Storek #define FSR_RP_S 1 /* extended => single */ 3855120Storek #define FSR_RP_D 2 /* extended => double */ 3955120Storek #define FSR_RP_80 3 /* extended => 80-bit */ 4055120Storek #define FSR_RP_SHIFT 28 4155120Storek #define FSR_RP_MASK 0x03 4255120Storek 4355120Storek #define FSR_TEM 0x0f800000 /* trap enable mask */ 4455120Storek #define FSR_TEM_SHIFT 23 4555120Storek #define FSR_TEM_MASK 0x1f 4655120Storek 4755120Storek #define FSR_NS 0x00400000 /* ``nonstandard mode'' */ 4855120Storek #define FSR_AU 0x00400000 /* aka abrupt underflow mode */ 4955120Storek #define FSR_MBZ 0x00300000 /* reserved; must be zero */ 5055120Storek 5155120Storek #define FSR_VER 0x000e0000 /* version bits */ 5255120Storek #define FSR_VER_SHIFT 17 5355120Storek #define FSR_VER_MASK 0x07 5455120Storek 5555120Storek #define FSR_FTT 0x0001c000 /* FP trap type */ 5655120Storek #define FSR_TT_NONE 0 /* no trap */ 5755120Storek #define FSR_TT_IEEE 1 /* IEEE exception */ 5855120Storek #define FSR_TT_UNFIN 2 /* unfinished operation */ 5955120Storek #define FSR_TT_UNIMP 3 /* unimplemented operation */ 6055120Storek #define FSR_TT_SEQ 4 /* sequence error */ 6155120Storek #define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 6255120Storek #define FSR_FTT_SHIFT 14 6355120Storek #define FSR_FTT_MASK 0x03 6455120Storek 6555120Storek #define FSR_QNE 0x00002000 /* queue not empty */ 6655120Storek #define FSR_PR 0x00001000 /* partial result */ 6755120Storek 6855120Storek #define FSR_FCC 0x00000c00 /* FP condition codes */ 6955120Storek #define FSR_CC_EQ 0 /* f1 = f2 */ 7055120Storek #define FSR_CC_LT 1 /* f1 < f2 */ 7155120Storek #define FSR_CC_GT 2 /* f1 > f2 */ 7255120Storek #define FSR_CC_UO 3 /* (f1,f2) unordered */ 7355120Storek #define FSR_FCC_SHIFT 10 7455120Storek #define FSR_FCC_MASK 0x03 7555120Storek 7655120Storek #define FSR_AX 0x000003e0 /* accrued exceptions */ 7755120Storek #define FSR_AX_SHIFT 5 7855120Storek #define FSR_AX_MASK 0x1f 7955120Storek #define FSR_CX 0x0000001f /* current exceptions */ 8055120Storek #define FSR_CX_SHIFT 0 8155120Storek #define FSR_CX_MASK 0x1f 8255120Storek 8355120Storek /* The following exceptions apply to TEM, AX, and CX. */ 8455120Storek #define FSR_NV 0x10 /* invalid operand */ 8555120Storek #define FSR_OF 0x08 /* overflow */ 8655120Storek #define FSR_UF 0x04 /* underflow */ 8755120Storek #define FSR_DZ 0x02 /* division by zero */ 8855120Storek #define FSR_NX 0x01 /* inexact result */ 8955120Storek 9055120Storek #endif /* _MACHINE_FSR_H_ */ 91