155148Storek /* 2*63320Sbostic * Copyright (c) 1992, 1993 3*63320Sbostic * The Regents of the University of California. All rights reserved. 455148Storek * 555148Storek * This software was developed by the Computer Systems Engineering group 655148Storek * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 755148Storek * contributed to Berkeley. 855148Storek * 955504Sbostic * All advertising materials mentioning features or use of this software 1055504Sbostic * must display the following acknowledgement: 1155504Sbostic * This product includes software developed by the University of 1259200Storek * California, Lawrence Berkeley Laboratory. 1355504Sbostic * 1455148Storek * %sccs.include.redist.c% 1555148Storek * 16*63320Sbostic * @(#)ctlreg.h 8.1 (Berkeley) 06/11/93 1755148Storek * 1859321Storek * from: $Header: ctlreg.h,v 1.6 93/04/27 14:29:07 torek Exp $ 1955148Storek */ 2055148Storek 2155148Storek /* 2255148Storek * Sun-4 (sort of) and 4c (Campus, i.e., SparcStation) control registers 2355148Storek * (includes address space definitions and registers in control space). 2455148Storek * 2555148Storek * Address space identifiers are 8 bits (0 through 255), but we 2655148Storek * only use four of them. 2755148Storek */ 2855148Storek 2955148Storek /* 0 unused */ 3055148Storek /* 1 unused */ 3155148Storek #define ASI_CONTROL 2 /* cache enable, context reg, etc */ 3255148Storek #define ASI_SEGMAP 3 /* segment maps (so we can reach each pmeg) */ 3355148Storek #define ASI_PTE 4 /* PTE space (pmegs) */ 3459321Storek #define ASI_HWFLUSHSEG 5 /* hardware assisted version of FLUSHSEG */ 3559321Storek #define ASI_HWFLUSHPG 6 /* hardware assisted version of FLUSHPG */ 3659321Storek #define ASI_HWFLUSHCTX 7 /* hardware assisted version of FLUSHCTX */ 3755148Storek #define ASI_USERI 8 /* I-space (user) */ 3855148Storek #define ASI_KERNELI 9 /* I-space (kernel) */ 3955148Storek #define ASI_USERD 10 /* D-space (user) */ 4055148Storek #define ASI_KERNELD 11 /* D-space (kernel) */ 4155148Storek #define ASI_FLUSHSEG 12 /* causes hardware to flush cache segment */ 4255148Storek #define ASI_FLUSHPG 13 /* causes hardware to flush cache page */ 4355148Storek #define ASI_FLUSHCTX 14 /* causes hardware to flush cache context */ 4455148Storek #ifdef SUN4 4555148Storek #define ASI_DCACHE 15 /* flush data cache; not used on 4c */ 4655148Storek #endif 4755148Storek /* 16 through 255 unused (and probably wrap, but who cares?) */ 4855148Storek 4955148Storek /* registers in the control space */ 5055148Storek #define AC_CONTEXT 0x30000000 /* context register (byte) */ 5155148Storek #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ 5255148Storek #define AC_CACHETAGS 0x80000000 /* cache tag base address */ 5355148Storek #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ 5455148Storek /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 5555148Storek 5655148Storek #ifdef SUN4 5755148Storek #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ 5855148Storek #define AC_BUS_ERR 0x60000000 /* bus error register */ 5955148Storek #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ 6055148Storek #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ 6155148Storek #endif 6255148Storek 6355148Storek #ifdef SUN4C 6455148Storek #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ 6555148Storek #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ 6655148Storek #define AC_ASYNC_ERR 0x60000008 /* async error reg */ 6755148Storek #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ 6855148Storek #define AC_CACHEDATA 0x90000000 /* cached data */ 6955148Storek 7055148Storek /* 7155148Storek * Bits in sync error register. Reading the register clears these; 7255148Storek * otherwise they accumulate. The error(s) occurred at the virtual 7355148Storek * address stored in the sync error address register, and may have 7455148Storek * been due to, e.g., what would usually be called a page fault. 7555148Storek * Worse, the bits accumulate during instruction prefetch, so 7655148Storek * various bits can be on that should be off. 7755148Storek */ 7855148Storek #define SER_WRITE 0x8000 /* error occurred during write */ 7955148Storek #define SER_INVAL 0x80 /* PTE had PG_V off */ 8055148Storek #define SER_PROT 0x40 /* operation violated PTE prot */ 8155148Storek #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 8255148Storek #define SER_SBUSERR 0x10 /* S-Bus bus error */ 8355148Storek #define SER_MEMERR 0x08 /* memory ecc/parity error */ 8455148Storek #define SER_SZERR 0x02 /* size error, whatever that is */ 8555148Storek #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 8655148Storek 8755148Storek #define SER_BITS \ 8855148Storek "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 8955148Storek 9055148Storek /* 9155148Storek * Bits in async error register (errors from DVMA or Sun-4 cache 9255148Storek * writeback). The corresponding bit is also set in the sync error reg. 9355148Storek * 9455148Storek * A writeback invalid error means there is a bug in the PTE manager. 9555148Storek * 9655148Storek * The word is that the async error register does not work right. 9755148Storek */ 9855148Storek #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 9955148Storek #define AER_TIMEOUT 0x20 /* bus timeout */ 10055148Storek #define AER_DVMAERR 0x10 /* bus error during DVMA */ 10155148Storek 10255148Storek #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 10355148Storek 10455148Storek #endif /* SUN4C */ 10555148Storek 10655148Storek /* 10755148Storek * Bits in system enable register. 10855148Storek */ 10955148Storek #define SYSEN_DVMA 0x20 /* enable dvma */ 11055148Storek #define SYSEN_CACHE 0x10 /* enable cache */ 11155148Storek #define SYSEN_RESET 0x04 /* reset the hardware */ 112