1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)fpu_subr.c 7.1 (Berkeley) 07/13/92 12 * 13 * from: $Header: fpu_subr.c,v 1.2 92/06/17 05:41:35 torek Exp $ 14 */ 15 16 /* 17 * FPU subroutines. 18 */ 19 20 #include "sys/types.h" 21 22 #include "machine/reg.h" 23 24 #include "fpu_arith.h" 25 #include "fpu_emu.h" 26 27 /* 28 * Shift the given number right rsh bits. Any bits that `fall off' will get 29 * shoved into the sticky field; we return the resulting sticky. Note that 30 * shifting NaNs is legal (this will never shift all bits out); a NaN's 31 * sticky field is ignored anyway. 32 */ 33 int 34 fpu_shr(register struct fpn *fp, register int rsh) 35 { 36 register u_int m0, m1, m2, m3, s; 37 register int lsh; 38 39 #ifdef DIAGNOSTIC 40 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 41 panic("fpu_rightshift 1"); 42 #endif 43 44 m0 = fp->fp_mant[0]; 45 m1 = fp->fp_mant[1]; 46 m2 = fp->fp_mant[2]; 47 m3 = fp->fp_mant[3]; 48 49 /* If shifting all the bits out, take a shortcut. */ 50 if (rsh >= FP_NMANT) { 51 #ifdef DIAGNOSTIC 52 if ((m0 | m1 | m2 | m3) == 0) 53 panic("fpu_rightshift 2"); 54 #endif 55 fp->fp_mant[0] = 0; 56 fp->fp_mant[1] = 0; 57 fp->fp_mant[2] = 0; 58 fp->fp_mant[3] = 0; 59 #ifdef notdef 60 if ((m0 | m1 | m2 | m3) == 0) 61 fp->fp_class = FPC_ZERO; 62 else 63 #endif 64 fp->fp_sticky = 1; 65 return (1); 66 } 67 68 /* Squish out full words. */ 69 s = fp->fp_sticky; 70 if (rsh >= 32 * 3) { 71 s |= m3 | m2 | m1; 72 m3 = m0, m2 = 0, m1 = 0, m0 = 0; 73 } else if (rsh >= 32 * 2) { 74 s |= m3 | m2; 75 m3 = m1, m2 = m0, m1 = 0, m0 = 0; 76 } else if (rsh >= 32) { 77 s |= m3; 78 m3 = m2, m2 = m1, m1 = m0, m0 = 0; 79 } 80 81 /* Handle any remaining partial word. */ 82 if ((rsh &= 31) != 0) { 83 lsh = 32 - rsh; 84 s |= m3 << lsh; 85 m3 = (m3 >> rsh) | (m2 << lsh); 86 m2 = (m2 >> rsh) | (m1 << lsh); 87 m1 = (m1 >> rsh) | (m0 << lsh); 88 m0 >>= rsh; 89 } 90 fp->fp_mant[0] = m0; 91 fp->fp_mant[1] = m1; 92 fp->fp_mant[2] = m2; 93 fp->fp_mant[3] = m3; 94 fp->fp_sticky = s; 95 return (s); 96 } 97 98 /* 99 * Force a number to be normal, i.e., make its fraction have all zero 100 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 101 * and (sometimes) for intermediate results. 102 * 103 * Internally, this may use a `supernormal' -- a number whose fp_mant 104 * is greater than or equal to 2.0 -- so as a side effect you can hand it 105 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0). 106 */ 107 void 108 fpu_norm(register struct fpn *fp) 109 { 110 register u_int m0, m1, m2, m3, top, sup, nrm; 111 register int lsh, rsh, exp; 112 113 exp = fp->fp_exp; 114 m0 = fp->fp_mant[0]; 115 m1 = fp->fp_mant[1]; 116 m2 = fp->fp_mant[2]; 117 m3 = fp->fp_mant[3]; 118 119 /* Handle severe subnormals with 32-bit moves. */ 120 if (m0 == 0) { 121 if (m1) 122 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32; 123 else if (m2) 124 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 125 else if (m3) 126 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 127 else { 128 fp->fp_class = FPC_ZERO; 129 return; 130 } 131 } 132 133 /* Now fix any supernormal or remaining subnormal. */ 134 nrm = FP_1; 135 sup = nrm << 1; 136 if (m0 >= sup) { 137 /* 138 * We have a supernormal number. We need to shift it right. 139 * We may assume m3==0. 140 */ 141 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */ 142 top >>= 1; 143 exp += rsh; 144 lsh = 32 - rsh; 145 m3 = m2 << lsh; 146 m2 = (m2 >> rsh) | (m1 << lsh); 147 m1 = (m1 >> rsh) | (m0 << lsh); 148 m0 = top; 149 } else if (m0 < nrm) { 150 /* 151 * We have a regular denorm (a subnormal number), and need 152 * to shift it left. 153 */ 154 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */ 155 top <<= 1; 156 exp -= lsh; 157 rsh = 32 - lsh; 158 m0 = top | (m1 >> rsh); 159 m1 = (m1 << lsh) | (m2 >> rsh); 160 m2 = (m2 << lsh) | (m3 >> rsh); 161 m3 <<= lsh; 162 } 163 164 fp->fp_exp = exp; 165 fp->fp_mant[0] = m0; 166 fp->fp_mant[1] = m1; 167 fp->fp_mant[2] = m2; 168 fp->fp_mant[3] = m3; 169 } 170 171 /* 172 * Concoct a `fresh' Quiet NaN per Appendix N. 173 * As a side effect, we set NV (invalid) for the current exceptions. 174 */ 175 struct fpn * 176 fpu_newnan(register struct fpemu *fe) 177 { 178 register struct fpn *fp; 179 180 fe->fe_cx = FSR_NV; 181 fp = &fe->fe_f3; 182 fp->fp_class = FPC_QNAN; 183 fp->fp_sign = 0; 184 fp->fp_mant[0] = FP_1 - 1; 185 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0; 186 return (fp); 187 } 188